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1.35v/1.5v registering clock driver with parity test and quad chip select 1 sste32882hlb 7201/14 datasheet 1.35v/1.5v registering clock driver with parity test and quad chip select sste32882hlb description this 28-bit 1:2, or 26-bit 1:2 a nd 4-bit 1:1, registering clock driver with parity is desi gned for 1.35v and 1.5v v dd operation. all inputs are 1.35v and 1.5v cmos compatible, except the reset (reset ) and mirror inputs which are lvcmos. all outputs are 1.35v and 1.5v cmos edge-controlled drivers optimized to drive single terminated 25 ? to 50 ? traces in ddr3 rdimm applications, except th e open-drain error (errout ) output. the clock outputs (yn and yn ) and control net outputs qncken, qncsn and qnodtn are desi gned with a different strength and skew to compensa te for different loading and equalize signal travel speed. the sste32882hlb has two basic modes of operation associated with the quad chip select enable (qcsen ) input. when the qcsen input pin is open (or pulled high), the component has two chip select inputs, dcs0 and dcs1 , and two copies of each chip select output, qacs0 , qacs1 , qbcs0 and qbcs1 . this is the "quadcs disabled" mode. when the qcsen input pin is pulled low, the component has four chip select inputs dcs[3:0] , and four chip select outputs, qcs[3:0] . this is the "quadcs enabled" mode. through the remainder of this specification, dcs[n:0] will indicate all of the chip select inputs, where n=1 for quadcs disabled, and n=3 for quadcs enabled. qxcs[n:0] will indicate all of the chip select outputs. the sste32882hlb includes a high-performance, low-jitter, low-skew buffer that distributes a differential clock input (ck and ck ) to four differential pairs of clock outputs (yn and yn ), and to one differential pair of feedback clock outputs (fbout and fbout ). the clock outputs are controlled by the input clocks (ck and ck ), the feedback clocks (fbin and fbin ), and the analog power inputs (av dd and av ss ). when av dd is grounded, the pll is turned off and bypassed for test purposes. the sste32882hlb operates from a differential clock (ck and ck ). data are registered at the crossing of ck going high, and ck going low. the data is either driven to the corresponding device outputs if exactly one of the dcs[n:0] input signals is driven low. based on the control register settings, the device can change its output characterisitics to match different dimm net topologies. the timing can be changed to comp ensate for differ ent flight time of signals within the target ap plication. by disabling unused outputs the power consumption is reduced. the sste32882hlb accepts a parity bit from the memory controller on the parity (par_in) input, compares it with the data received on the dimm-independent data inputs (dan, dban, dras , dcas , and dwe ), and indicates whether a parity error has occurred on the open-drain errout pin (active low). the convention is even parity; i.e., valid parity is defined as an even number of ones across the dimm-independent data inputs combined with the parity input bit. to calculate parity, all dimm-independent d-inputs must be tied to a known logic state. the dimm-dependent signal s (dcken, dodtn, and dcsn ) are not included in the pa rity check computation. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power-up. the sste32882hlb is available in a 176-ball bga with 0.65mm ball pitch in a 11 x 20 grid. it is also available in a 176-ball thin-profile fine-pitch bga with 0.65mm ball pitch in an 8x22 grid. the device pinout supports outputs on the outer two left and right columns to support easy dimm signal routing. corresponding inputs are placed in a-way that two devices can be placed back-to-back for four rank modules while the data inputs share the same vias. each input a nd output is located close to an associated no ball position or on the outer two rows to allow low cost via technology combined with the small 0.65mm ball pitch.
1.35v/1.5v registering clock driver with parity test and quad chip select 2 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature features ? pinout optimizes ddr3 rdimm pcb layout ? 1-to-2 register outputs and 1-to-4 clock pair outputs support stacked ddr3 rdimms ? phase lock loop clock driver for buffering one differen tial clock pair (ck and ck ) and distributing to four differential outputs ? supports lvcmos switching levels on the reset and mirror inputs ? checks priority on dimm-independent data inputs ? supports dynamic 1t/3t timing transaction and output inversion feature for improved timing performance during normal operations and mrs command pass-through ? supports cke power down operation modes ? supports quad chip se lect operation features ? reset input disables differential input reci evers, resets all registers, and disa bles all output dr ivers except errout and qncken ? provides access to internal control words for configuring the device f eatures and adapting in di fferent rdimm and system applications ? latch-up performance exceeds 100ma ? esd > 2000v per mil-std883, method 3015; esd > 200v using machine model (c = 200pf, r = 0) ? available in 176 ball grid array package
1.35v/1.5v registering clock driver with parity test and quad chip select 3 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature block diagram - register and pl l logic diagram (positive logic) 1 dcs[n:0] indicates all of the chip select i nputs, where n=1 for quadcs disabled, and n=3 for quadcs enabled. qxcs[n:0] indicates all of the chip select outputs. da3..da9, da10, da12, 3 4 da0..da2, dba2 da3, da4, dba0, dba1 control word state machine and control logic dcs[n:0] dcke0, dodt0, dcke1 dodt1 pll r d q ce r d q ce r d q r d q r d q 0 1 0 1 0 1 0 1 pre- launch cmr access da11, da13..da15, dba0..dba2 dras , dcas , dwe output inversion 4 a-enable b-enable y0..y3- enable v ref qxa3..qxa9, qxa11, qxa13..qxa15, qxba0..qxba2 qxa10, qxcas , qxwe qxa12, qxras , qacken qaodtn qbcken qbodtn y1 y1 y0 y0 y2 y2 fbout fbout y3 y3 ck ck fbin fbin reset 1/4 ck delay 1/4 ck delay 1/4 ck delay 10k ? ~100k ? oe0 oe1 oe2 oe3 1/4 ck 0 1 delay qxcs[n:0] da0-da2, qxa0-qxa2, dras dcas dwe (1) (1) cs logic
1.35v/1.5v registering clock driver with parity test and quad chip select 4 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature block diagram - parity logic diagram (positive logic) 1 dcs[n:0] indicates all of the chip select i nputs, where n=1 for quadcs disabled, and n=3 for quadcs enabled. qxcs[n:0] indicates all of the chip select outputs. internal logic dcke0, dcke1 dodt0, dodt1 reset ck ck fbin fbin pll d r q d r q fbout fbout y3 y3 y1 y0 y2 y2 y1 y0 internal logic internal logic qacken qbcken qaodtn qbodtn 10k ? - 100k ? v ref da0..da15, dba0..dba2, dras, dcas, dwe par_in dcs[n:0] d r q d r q d r q internal logic internal logic qa0..qa15, qba0..qba2, qras, qcas, qwe errout qxcs[n:0] ce ce parity generator and error check dras dcas dwe output inversion disabled 3t timing enabled cs logic (1) (1)
1.35v/1.5v registering clock driver with parity test and quad chip select 5 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature pinout configuration package options include a 176-ball thin-profile fine-pitch bga (t fbga) with 0.65mm ball pitch, 11 x 20 grid, 8.0mm x 13.5mm. it uses the mechanical outline mo-246 variation f. the device pinout supports outputs on the outer two left and right columns to s upport easy dimm signal routing. corresponding inputs are placed in a way that two devices can be placed back to back for 4 rank modul es while the data inputs share the same vias. each input and output is located close to an associat ed no-ball position or on the o uter two rows to allow low cost via technology combined with the small 0.65mm ball pitch. 176-ball thin profile fine pitch bga (tfbga) 11x20 grid top view a b c d e f g h j k l m n p r t u v w y 123 4 5 67 8 91011
1.35v/1.5v registering clock driver with parity test and quad chip select 6 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature pin descriptions the device has symmetric pinout with the inputs on the south side and the outputs on the east and west sides. this allows back-to-back mounting on both sides of the pcb if more than one device is needed. ball assignment: mirror = low, qcsen = high or float this table specifies the pinout for sste32882hlb in the front configuration (quadcs mode disabled). balls a9 and w7 are reserved for future functions and must no t be connected on the system. however, a ball on the device and connecting pad on the module are required in these locations. also, balls y2 and r6 are ?do not use? balls reserved for dcs2 and dcs3 in the quadcs mode, and must not be connected on the system. the device is designed to tolerate floating on these pins. blank spaces indicate no ball is populated at that gri dpoint, and vias on the module may be located in these areas. 1 2 345 6 7 891011 a qaa13 qaa8 qcsen v ss reset mirror errout v ss rsvd qba8 qba13 b qaa14 qaa7 qba7 qba14 c qaa9 qaa6 v dd v dd v dd v dd v dd qba6 qba9 d qaa11 qaa5 v ss v ss v ss v ss v ss qba5 qba11 e qaa2 qaa4 v dd v dd v dd v dd v dd qba4 qba2 f qaa1 qaa3 v ss v ss v ss v ss v ss qba3 qba1 g qaa0 qaba1 v dd v dd v dd v dd v dd qbba1 qba0 h qaa12 qaba0 v ss v ss v ss v ss v ss qbba0 qba12 j qaba2 qacs1 v dd v dd v dd v dd v dd qbcs1 qbba2 k qaa15 qacke0 v ss v ss v ss v ss v ss qbcke0 qba15 lqawe qacs0 v dd v dd v dd v dd v dd qbcs0 qbwe m qaa10 qacke1 v ss v ss v ss v ss v ss qbcke1 qba10 n qacas qaodt0 v dd v dd v dd v dd v dd qbodt0 qbcas p qaras qaodt1 da3 v ss v ss v ss da4 qbodt1 qbras r dcke1 da14 da15 da5 rsvd da2 da1 da10 dodt1 tdcke0dcs0 dcs1 dodt0 u da12 dba2 y1 pv ss v dd pv dd y0 da13 dcas v da9 da11 y1 pv ss v ss pv dd y0 dras dwe w da8 da6 fbin y3 av ss ck rsvd y2 fbout da0 dba0 y da7 rsvd fbin y3 av dd ck vrefca y2 fbout par_in dba1
1.35v/1.5v registering clock driver with parity test and quad chip select 7 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ball assignment: mirror = high, qcsen = high or float this table specifies the pinout for sste32882hlb in the back configuration (quadcs mode disabled). balls a9 and w7 are reserved for future functions and must no t be connected on the system. however, a ball on the device and connecting pad on the module are required in these locations. also, balls y10 and r6 are ?do not use? balls reserved for dcs2 and dcs3 in the quadcs mode, and must not be connected on the system. the device is designed to tolerate floating on these pins. blank spaces indicate no ball is populated at that gri dpoint, and vias on the module may be located in these areas. 12 345 6 7 891011 a qaa13 qaa8 qcsen v ss reset mirror errout v ss rsvd qba8 qba13 b qaa14 qaa7 qba7 qba14 c qaa9 qaa6 v dd v dd v dd v dd v dd qba6 qba9 d qaa11 qaa5 v ss v ss v ss v ss v ss qba5 qba11 e qaa2 qaa4 v dd v dd v dd v dd v dd qba4 qba2 f qaa1 qaa3 v ss v ss v ss v ss v ss qba3 qba1 g qaa0 qaba1 v dd v dd v dd v dd v dd qbba1 qba0 h qaa12 qaba0 v ss v ss v ss v ss v ss qbba0 qba12 j qaba2 qacs1 v dd v dd v dd v dd v dd qbcs1 qbba2 k qaa15 qacke0 v ss v ss v ss v ss v ss qbcke0 qba15 lqawe qacs0 v dd v dd v dd v dd v dd qbcs0 qbwe m qaa10 qacke1 v ss v ss v ss v ss v ss qbcke1 qba10 n qacas qaodt0 v dd v dd v dd v dd v dd qbodt0 qbcas p qaras qaodt1 da4 v ss v ss v ss da3 qbodt1 qbras r dodt1 da10 da1 da2 rsvd da5 da15 da14 dcke1 t dodt0 dcs1 dcs0 dcke0 udcas da13 y1 pv ss v dd pv dd y0 dba2 da12 vdwe dras y1 pv ss v ss pv dd y0 da11 da9 w dba0 da0 fbin y3 av ss ck rsvd y2 fbout da6 da8 y dba1 par_in fbin y3 av dd ck vrefca y2 fbout rsvd da7
1.35v/1.5v registering clock driver with parity test and quad chip select 8 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ball assignment: mirror = low, qcsen = low this table specifies the pinout for sste32882hlb in the front configuration (quadcs mode enabled). balls a9 and w7 are reserved for future functions and must no t be connected on the system. however, a ball on the device and connecting pad on the module are required in these locations. blank spaces indicate no ba ll is populated at that gridpoint, and vias on the module may be located in these areas. 1 2 345 6 7 891011 a qaa13 qaa8 qcsen v ss reset mirror errout v ss rsvd qba8 qba13 b qaa14 qaa7 qba7 qba14 c qaa9 qaa6 v dd v dd v dd v dd v dd qba6 qba9 d qaa11 qaa5 v ss v ss v ss v ss v ss qba5 qba11 e qaa2 qaa4 v dd v dd v dd v dd v dd qba4 qba2 f qaa1 qaa3 v ss v ss v ss v ss v ss qba3 qba1 g qaa0 qaba1 v dd v dd v dd v dd v dd qbba1 qba0 h qaa12 qaba0 v ss v ss v ss v ss v ss qbba0 qba12 j qaba2 qcs1 v dd v dd v dd v dd v dd qcs3 qbba2 k qaa15 qacke0 v ss v ss v ss v ss v ss qbcke0 qba15 lqawe qcs0 v dd v dd v dd v dd v dd qcs2 qbwe m qaa10 qacke1 v ss v ss v ss v ss v ss qbcke1 qba10 n qacas qaodt0 v dd v dd v dd v dd v dd qbodt0 qbcas p qaras qaodt1 da3 v ss v ss v ss da4 qbodt1 qbras r dcke1 da14 da15 da5 dcs3 da2 da1 da10 dodt1 tdcke0dcs0 dcs1 dodt0 u da12 dba2 y1 pv ss v dd pv dd y0 da13 dcas v da9 da11 y1 pv ss v ss pv dd y0 dras dwe w da8 da6 fbin y3 av ss ck rsvd y2 fbout da0 dba0 y da7 dcs2 fbin y3 av dd ck vrefca y2 fbout par_in dba1
1.35v/1.5v registering clock driver with parity test and quad chip select 9 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ball assignment: mirror = high, qcsen = low this table specifies the pinout for sste32882hlb in the back configuration (quadcs mode enabled). balls a9 and w7 are reserved for future functions and must no t be connected on the system. however, a ball on the device and connecting pad on the module are required in these locations. bla nk spaces indicate no ball is popul ated at that gridpoint, and vias on the module may be located in these areas. 12 345 6 7 891011 a qaa13 qaa8 qcsen v ss reset mirror errout v ss rsvd qba8 qba13 b qaa14 qaa7 qba7 qba14 c qaa9 qaa6 v dd v dd v dd v dd v dd qba6 qba9 d qaa11 qaa5 v ss v ss v ss v ss v ss qba5 qba11 e qaa2 qaa4 v dd v dd v dd v dd v dd qba4 qba2 f qaa1 qaa3 v ss v ss v ss v ss v ss qba3 qba1 g qaa0 qaba1 v dd v dd v dd v dd v dd qbba1 qba0 h qaa12 qaba0 v ss v ss v ss v ss v ss qbba0 qba12 j qaba2 qcs1 v dd v dd v dd v dd v dd qcs3 qbba2 k qaa15 qacke0 v ss v ss v ss v ss v ss qbcke0 qba15 lqawe qcs0 v dd v dd v dd v dd v dd qcs2 qbwe m qaa10 qacke1 v ss v ss v ss v ss v ss qbcke1 qba10 n qacas qaodt0 v dd v dd v dd v dd v dd qbodt0 qbcas p qaras qaodt1 da4 v ss v ss v ss da3 qbodt1 qbras r dodt1 da10 da1 da2 dcs3 da5 da15 da14 dcke1 t dodt0 dcs1 dcs0 dcke0 udcas da13 y1 pv ss v dd pv dd y0 dba2 da12 vdwe dras y1 pv ss v ss pv dd y0 da11 da9 w dba0 da0 fbin y3 av ss ck rsvd y2 fbout da6 da8 y dba1 par_in fbin y3 av dd ck vrefca y2 fbout dcs2 da7
1.35v/1.5v registering clock driver with parity test and quad chip select 10 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature pinout configuration narrow package 1 as an option, the device is available as a176-ball thin-profile fine-pitch bga (tfbga) with 0.65mm ball pitch, 8 x 22 grid, 6.0mm x 15mm. it is using the mechanical outline mo-246 variation b. equivalent to the 11 x 20 grid configuration the device pinout supports outputs on the outer two left and right columns. corresponding inputs are placed in a way that two devices can be placed back to back for 4 rank modules while the data inputs share the same vias. 176-ball thin profile fine pitch bga (tfbga) 8x22 grid top view 1. this package may only be used in new dimm designs. it is not intended for use in the existing dimm?s. 12345678 a b c d e f g h j k l m n p r t u v w y aa ab
1.35v/1.5v registering clock driver with parity test and quad chip select 11 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ball assignment; mirror=low, qcsen =high (or float) the table below specifies the pinout for sste32882 in front configuration with quadcs mode disabled. the device has symmetric pinout with inputs at the south side and outputs to east and west sides. this allows back to back mounting on both sides of the pcb if more than one device is needed. 12345678 a qaa13 qaa8 qcsen reset errout rsvd qba8 qba13 b qaa14 qaa7 vss vss mirror vss qba7 qba14 c qaa9 qaa6 vdd vdd vdd vdd qba6 qba9 d qaa11 qaa5 vss vss vss vss qba5 qba11 e qaa2 qaa4 vdd vdd vdd vdd qba4 qba2 f qaa1 qaa3 vss vss vss vss qba3 qba1 g qaa0 qaba1 vdd vdd vdd vdd qbba1 qba0 h qaa12 qaba0 vss vss vss vss qbba0 qba12 j qaba2 qacs1 vdd vdd vdd vdd qbcs1 qbba2 k qaa15 qacke0 vss vss vss vss qbcke0 qba15 l qawe qacs0 vdd vdd vdd vdd qbcs0 qbwe m qaa10 qacke1 vss vss vss vss qbcke1 qba10 n qacas qaodt0 vdd vdd vdd vdd qbodt0 qbcas p qaras qaodt1 vss vss vss vss qbodt1 qbras r da14 dcke1 vdd vdd vdd vdd dodt1 da10 t dcs0 dcke0 vss vss vss vss dodt0 dcs1 u da12 da3 y1 pvss pvdd y0 da4 dcas v da5 da9 y1 pvss pvdd y0 dwe da2 w da8 da15 y3 pvss pvdd y2 da1 dba0 y da7 dba2 y3 avss avdd y2 da13 dba1 aa da11 rsvd fbin ck rsvd fbout par_in dras ab da6 rsvd fbin ck vrefca fbout rsvd da0 pins a6, aa2, aa5, ab2 and ab7 are reserved for future functions must not be connected on system. the system must provide a solder pa d for these pins. the device design needs to tolerate floating on these pins. a3 may be left floating since it has an internal pull-up resistor.
1.35v/1.5v registering clock driver with parity test and quad chip select 12 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ball assignment; mi rror=high, qcsen =high (or float) the table below specifies the pinout for sste32882 in back configuration with quadcs mode disabled. 12345678 a qaa13 qaa8 qcsen reset errout rsvd qba8 qba13 b qaa14 qaa7 vss vss mirror vss qba7 qba14 c qaa9 qaa6 vdd vdd vdd vdd qba6 qba9 d qaa11 qaa5 vss vss vss vss qba5 qba11 e qaa2 qaa4 vdd vdd vdd vdd qba4 qba2 f qaa1 qaa3 vss vss vss vss qba3 qba1 g qaa0 qaba1 vdd vdd vdd vdd qbba1 qba0 h qaa12 qaba0 vss vss vss vss qbba0 qba12 j qaba2 qacs1 vdd vdd vdd vdd qbcs1 qbba2 k qaa15 qacke0 vss vss vss vss qbcke0 qba15 l qawe qacs0 vdd vdd vdd vdd qbcs0 qbwe m qaa10 qacke1 vss vss vss vss qbcke1 qba10 n qacas qaodt0 vdd vdd vdd vdd qbodt0 qbcas p qaras qaodt1 vss vss vss vss qbodt1 qbras r da10 dodt1 vdd vdd vdd vdd dcke1 da14 t dcs1 dodt0 vss vss vss vss dcke0 dcs0 u dcas da4 y1 pvss pvdd y0 da3 da12 v da2 dwe y1 pvss pvdd y0 da9 da5 w dba0 da1 y3 pvss pvdd y2 da15 da8 y dba1 da13 y3 avss avdd y2 dba2 da7 aa dras pa r_in fbin ck rsvd fbout rsvd da11 ab da0 rsvd fbin ck vrefca fbout rsvd da6 pins a6, aa5, aa7, ab2 and ab7 are reserved for future functions must not be connected on system. the system must provide a solder pad for these pins. the device design needs to tolerate floating on these pins. a3 may be left floating since it has an internal pull-up resistor.
1.35v/1.5v registering clock driver with parity test and quad chip select 13 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ball assignment; mirror=low, qcsen =low the table below specifies the pinout for sste32882 in front configuration with quadcs mode enabled. 12345678 a qaa13 qaa8 qcsen reset errout rsvd qba8 qba13 b qaa14 qaa7 vss vss mirror vss qba7 qba14 c qaa9 qaa6 vdd vdd vdd vdd qba6 qba9 d qaa11 qaa5 vss vss vss vss qba5 qba11 e qaa2 qaa4 vdd vdd vdd vdd qba4 qba2 f qaa1 qaa3 vss vss vss vss qba3 qba1 g qaa0 qaba1 vdd vdd vdd vdd qbba1 qba0 h qaa12 qaba0 vss vss vss vss qbba0 qba12 j qaba2 qcs1 vdd vdd vdd vdd qcs3 qbba2 k qaa15 qacke0 vss vss vss vss qbcke0 qba15 l qawe qcs0 vdd vdd vdd vdd qcs2 qbwe m qaa10 qacke1 vss vss vss vss qbcke1 qba10 n qacas qaodt0 vdd vdd vdd vdd qbodt0 qbcas p qaras qaodt1 vss vss vss vss qbodt1 qbras r da14 dcke1 vdd vdd vdd vdd dodt1 da10 t dcs0 dcke0 vss vss vss vss dodt0 dcs1 u da12 da3 y1 pvss pvdd y0 da4 dcas v da5 da9 y1 pvss pvdd y0 dwe da2 w da8 da15 y3 pvss pvdd y2 da1 dba0 y da7 dba2 y3 avss avdd y2 da13 dba1 aa da11 dcs2 fbin ck rsvd fbout par_in dras ab da6 rsvd fbin ck vrefca fbout dcs3 da0 pins a6, aa5 and ab2 are reserved for future functions must not be connected on system. the system must provide a solder pad for these pins. the device de sign needs to tolerate floating on these pins. a3 must be tied low fo r this configuration.
1.35v/1.5v registering clock driver with parity test and quad chip select 14 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ball assignment; mi rror=high, qcsen =low) the table below specifies the pinout for sste32882 in back configuration with quadcs mode enabled. . 12345678 a qaa13 qaa8 qcsen reset errout rsvd qba8 qba13 b qaa14 qaa7 vss vss mirror vss qba7 qba14 c qaa9 qaa6 vdd vdd vdd vdd qba6 qba9 d qaa11 qaa5 vss vss vss vss qba5 qba11 e qaa2 qaa4 vdd vdd vdd vdd qba4 qba2 f qaa1 qaa3 vss vss vss vss qba3 qba1 g qaa0 qaba1 vdd vdd vdd vdd qbba1 qba0 h qaa12 qaba0 vss vss vss vss qbba0 qba12 j qaba2 qcs1 vdd vdd vdd vdd qcs3 qbba2 k qaa15 qacke0 vss vss vss vss qbcke0 qba15 l qawe qcs0 vdd vdd vdd vdd qcs2 qbwe m qaa10 qacke1 vss vss vss vss qbcke1 qba10 n qacas qaodt0 vdd vdd vdd vdd qbodt0 qbcas p qaras qaodt1 vss vss vss vss qbodt1 qbras r da10 dodt1 vdd vdd vdd vdd dcke1 da14 t dcs1 dodt0 vss vss vss vss dcke0 dcs0 u dcas da4 y1 pvss pvdd y0 da3 da12 v da2 dwe y1 pvss pvdd y0 da9 da5 w dba0 da1 y3 pvss pvdd y2 da15 da8 y dba1 da13 y3 avss avdd y2 dba2 da7 aa dras pa r_in fbin ck rsvd fbout dcs2 da11 ab da0 rsvd fbin ck vrefca fbout dcs3 da6 pins a6, aa5 and ab2 are reserved for future functions must not be connected on system. the system must provide a solder pad for thes e pins. the device design n eeds to tolerate floating on these pins. a3 must be tied low for this configuration.
1.35v/1.5v registering clock driver with parity test and quad chip select 15 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature terminal functions signal group signal name type description ungated inputs dcken, dodtn 1.35v/1.5v cmos inputs 1 dram corresponding register function pins not associated with chip select. chip select gated inputs dan, dban, dras , dcas , dwe 1.35v/1.5v cmos inputs 1 dram corresponding register inputs, re-driven only when either chip select is low. if both chip selects are low the register maintains the state of the previous input clock cycle at its outputs chip select inputs dcs0 , dcs1 1.35v/1.5v cmos inputs 1 dram corresponding register chip select signals. these pins initiate dram address/command dec odes, and as such exactly one will be low when a valid address/command is present which should be re-driven. dcs2 , dcs3 1.35v/1.5v cmos inputs 1 dram corresponding register chip select signals when quadcs mode is enabled. dcs2 and dcs3 inputs are disabled when quadcs mode is disabled. re-driven outputs qxan, qxban, qxcsn , qxcken, qxodtn, qxras , qxcas , qxwe 1.35v/1.5v cmos outputs 2 outputs of the register, valid af ter the specified clock count and immediately following a rising edge of the clock. x is a or b; outputs are grouped as a or b and may be enabled or disabled via rc0. parity input par_in 1.35v/1.5v cmos inputs 1 input parity is received on pin pa r_in and should maintain parity across the chip select gated inputs (see above), at the rising edge of the input clock, one input clock cycle after corresponding data and one or both chip selects are low. parity error output errout open drain when low, this output indi cates that a parity error was identified associated with th e address and/or command inputs. errout will be active for two clock cycles, and delayed by 3 clock cycles to the corresponding input data clock inputs ck, ck 1.35v/1.5v cmos inputs 1 differential master clock input pair to the pll; has weak internal pull-down resistors (10k ? ~100k ??? . feedback fbin, fbin 1.35v/1.5v cmos inputs 1 feedback clock input clock fbout, fbout 1.35v/1.5v cmos outputs 2 feedback clock output clock outputs yn, yn 1.35v/1.5v cmos outputs 2 re-driven clock miscellaneous inputs reset cmos 3 active low asynchronous reset input. when low, it causes a reset of the internal latches and disables the outputs, thereby forcing the outputs to float. once reset becomes high the q outputs get enabled and are driven low (errout is driven high) until the first access has been performed. reset also resets the errout signal. mirror cmos 3 selects between two different ballouts for front or back operation. when the mirror input is high, the device input bus termination (ibt) is turned off on all inputs, except the dcsn and dodtn inputs. qscen cmos 3 enables the quadcs mode. the qscen input has a weak internal pullup resistor (10k ? - 100k ? ).
1.35v/1.5v registering clock driver with parity test and quad chip select 16 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature function table (each flip flop ) with quadcs mode disabled power vrefca 1 reference voltage input reference voltag e for the differential data inputs, v dd /2 (0.75v) nominal. vdd register power power supply voltage (register) vss register ground ground (register) avdd analog power analog supply voltage (pll) avss analog ground analog ground (pll) pvdd pll power clock logic and clock output driver power supply (pll) pvss pll ground clock logic and clock output driver ground (pll) rsvd i/o reserved pins, must be left floating (pll) 1 1.35v/1.5v cmos inputs use v refca as the switching point refe rence for these recievers. 2 these outputs are optimized for memory applications to drive dram inputs to 1.35v/1.5v signaling levels. 3 voltage levels according standard jesd 8-11a, wide range, non terminated logic. inputs outputs 1 1 q 0 means the output does not change state. reset dcs0 dcs1 ck 2 2 it is illegal to hold both the ck and ck inputs at static logic high levels or static complementar y logic levels (low and high) when reset is driven high. ck 2 addr 3 3 addr = da[15:0], dba[2:0] cmd 4 4 cmd = dras , dcas , dwe . ctrl 5 5 ctrl = dodtn, dcken. qn 6 6 qn = qxan, qxras , qxcas , qxwe , and qxban. qxcs0 qxcs1 qxodtn qxcken hll ?? control word control word control word q 0 hh q 0 q 0 h x x l or h h or l x x x q 0 q 0 q 0 q 0 q 0 hlh ?? xxx follows input lh follows input follows input h x x l l x x x float float float float l hhl ?? xxx follows input hl follows input follows input hhh ?? x or float x or float x q 0 or float 7 7 depending on control word rc0 bit da4. if rc0 da4 is cleared, previous state (q 0 ) is maintained. address floating is disabled independent of control wo rd rc0 once 3t timing is activated. hh follows input follows input l x or float x or float x or float x or float x or float x or float x or float float float float float l signal group signal name type description
1.35v/1.5v registering clock driver with parity test and quad chip select 17 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature function table (each flip flop ) with quadcs mode enabled inputs outputs reset dcs[3:0] ck 1 1 it is illegal to hold both the ck and ck inputs at static logic high levels or static complementary logic levels (low and high) when reset is driven high. ck 1 a/c/e 2 2 a/c/e = da0..da15, dba0..dba2, dras , dcas , dwe , dodtn, dcken qn qcs[3:0] qxodtn qxcken h llhh ? ? control word no change hhhh no change no change hhhll hllll h xxxx l or h h or l x no change no change no change no change h lhhh ?? dn dn lhhh dodtn dcken hhlhh ?? dn dn hlhh dodtn dcken hhhlh ?? dn dn hhlh dodtn dcken hhhhl ?? dn dn hhhl dodtn dcken hlhlh ?? dn dn lhlh dodtn dcken hhllh ?? dn dn hllh dodtn dcken hlhhl ?? dn dn lhhl dodtn dcken hhlhl ?? dn dn hlhl dodtn dcken h xxxx ll x float float float l h hhhh ?? x no change or float 3 3 depending on control word rc0 bit da4. if rc0 da4 is cleared, previous state is maintained. address floating is disabled independent of control word rc0 once 3t timing is activated hhhh dodtn dcken h lllh ?? x ilegal input states hllhl hlhll hhlll l x or float x or float x or float x or float float float float l
1.35v/1.5v registering clock driver with parity test and quad chip select 18 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature parity, low power and standby with quadcs mode disabled inputs output reset dcs0 dcs1 ck 1 1 it is illegal to hold both the ck and ck inputs at static logic high levels or static complementary logic levels (low and high) when reset is driven high. ck 1 ? of c/a 2 2 c/a= dan, dban, dras , dcas , dwe . inputs dcken, dodtn, and dcsn are not included in this range. this column represents the sum of the number of c/a signals that are electrically high. par_in 3 3 par_in arrives one clock cycle after the data to which it applies, errout is issued three clock cycles after the failing data. errout 4 4 this transition assumes errout is high at the crossing of ck going high and ck going low. if errout is low, it stays latched low for exactly two clock cycles or until reset is driven low. hlx ?? even l h hlx ?? odd l l hlx ?? even h l hlx ?? odd h h hxl ?? even l h hxl ?? odd l l hxl ?? even h l hxl ?? odd h h hhh ?? xx h 5 5 same three cycle delay for errout is valid for the de-select phase (see diagram) h x x l or h h or l x x errout 0 hxxl l x x h 6 6 the system is not allowed to pull ck and ck low while errout is asserted. l x or floating x or floating x or floating x or floating x or floating x or floating h
1.35v/1.5v registering clock driver with parity test and quad chip select 19 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature parity, low power and standby with quadcs mode enabled inputs output reset dcs[3:0] ck 1 1 it is illegal to hold both the ck and ck inputs at static logic high levels or static complementary logic levels (low and high) when reset is driven high. ck 1 ? of a/c 2 2 a/c = da0..da15, dba0..dba2, dras , dcas , dwe . inputs dcke0, dcke1, dodt0, dodt1, dcs0 and dcs1 are not included in this range. this column represen ts the sum of the number of a/c signals that are elec- trically high. par_in 3 3 par_in arrivesone clock cycle af terdata to which it applies, errout is issued three clock cycles after the fail- ing data. errout 4 4 this transition assumes errout is high at the crossing of ck going high and ck going low. if errout is low, it stays latched low for exactly two clock cycles or until reset is driven low. hlxxx xlxx xxlx xxxl ?? even l h hlxxx xlxx xxlx xxxl ?? odd l l hlxxx xlxx xxlx xxxl ?? even h l hlxxx xlxx xxlx xxxl ?? odd h h h hhhh ?? xx h 5 5 same three-cycle delay for errout is valid for the de-select phase (see diagram) h xxxx l or h h or l x x errout n 0 h xxxx l l x x h 6 6 the system is not allo wed to pull ck and ck low while errout is asserted. l x or floating x or floating x or floating x or floating x or floating h
1.35v/1.5v registering clock driver with parity test and quad chip select 20 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature pll function table inputs outputs pll reset av dd oen 1 1 the output enable (oen) to disable the output buffer is not an input signal to the sste32882hlb, but an internal signal from the pll powerdown control and test logic. it is controlled by setting or clearing the corresponding bit in the clock drive r mode register. ck 2 2 it is illegal to hold both the ck and ck inputs at static logic high levels or static complementary logic levels (low and high) when reset is driven high. ck 2 yn yn fb out fb out l x x x x float float float float off h vdd nominal l l h l hl hon h vdd nominal l h l h l h l on h vdd nominal h l h float float l hon h vdd nominal h h l float float h lon h vdd nominal x l l float float float float off h gnd 3 3 this is a device test mode and all regi ster timing parameters are not guaranteed. llh l hl h bypassed/off h gnd 3 lhl h lh l bypassed/off h gnd 3 h l h float float l h bypassed/off h gnd 3 h h l float float h l bypassed/off h gnd 3 x l l float float float float bypassed/off h x x h h reserved
1.35v/1.5v registering clock driver with parity test and quad chip select 21 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ex posure to absolute maximum rating conditions for extended periods may affect reliability dc and ac specifications the sste32882hlb parametric values are specified for the device default control word settings, unless otherwise stated. note th at rc10 setting does not affect an y of the paramteric values. symbol parameter conditions min max unit av dd , pv dd , v dd supply voltage ?0.4 +1.975 v v i receiver input voltage 1 1 the input and output negative-voltage ratings may be ex ceeded if the input and outpu t clamp-current ratings are observed. this value is limited to 1.975 v maximum. ?0.4 v dd +0.5 v v ref reference voltage ?0.4 v dd +0.5 v v o driver output voltage 1 ?0.4 v dd +0.5 v i ik input clamp current v i < 0 or v i > v dd -50 ma i ok output clamp current v o < 0 or v o > v dd 50 ma i o continuous output current 0 < v o < v dd 50 ma i ccc continuous current through each v dd or gnd pin 100 ma t stg storage temperature ?65 +150 ? c r ? ja package thermal impedance, junction-to-ambient 2 2 the package thermal impedance is ca lculated in accord ance with jesd51-2. 0m/s airflow 43.8 ? c/w 1m/s airflow 35.5 r ? jb package thermal impedance, junction-to-board 2 22 ? c/w r ? jc package thermal impedance, junction-to-case 2 16.2 ? c/w
1.35v/1.5v registering clock driver with parity test and quad chip select 22 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature dc specifications - voltage the sste32882 parametric values are spec ified for the device defau lt control word settings, unl ess otherwise stated. note that the rc10 setting does not affe ct any of the parametric values. symbol parameter signals min nom max unit v dd dc supply voltage (1.5v operation) 1.425 1.5 1.575 v dc supply voltage (1.35v operation) 1.282 1.35 1.451 v v ref dc reference voltage 0.49 x v dd 0.50 x v dd 0.51 x v dd v v tt dc termination voltage v ref ? 40 mv v ref v ref + 40 mv v v ih(ac) ac high-level input volt age (1.5v operation, ddr3-800/1066/1333) data inputs 1 v ref + 175 mv ? v dd + 0.4 v ac high-level input voltage (1.5v operation, ddr3-1600) data inputs 1 v ref + 150 mv ? v dd + 0.4 v ac high-level input volt age (1.35v operation, ddr3l-800/1066/1333) data inputs 1 v ref + 150 mv ? v dd + 0.2 v ac high-level input voltage (1.35v operation, ddr3l-1600) data inputs 1 v ref + 135 mv ? v dd + 0.2 v v il(ac) ac low-level input volta ge (1.5v operation, ddr3-800/1066/1333) data inputs 1 ?0.4 ? v ref ? 175 mv v ac low-level input voltage (1.5v operation, ddr3-1600) data inputs 1 ?0.4 ? v ref ? 150 mv v ac low-level input volta ge(1.35v operation, ddr3l-800/1066/1333) data inputs 1 ?0.2 ? v ref ? 150 mv v ac low-level input voltage (1 .35v operation, ddr3l-1600) data inputs 1 ?0.2 ? v ref ? 135 mv v v ih(dc) dc high-level input voltage(1.5v operation) data inputs 1 v ref + 100 mv ? v dd + 0.4 v dc high-level input voltage(1.35v operation) data inputs 1 v ref + 90 mv ? v dd + 0.2 v v il(dc) dc low-level input vo ltage(1.5v operation) data inputs 1 ?0.4 ? v ref ? 100 mv v dc low-level input vo ltage(1.35v operation) data inputs 1 ?0.2 ? v ref ? 90 mv v v ih(cmo s) high-level input voltage cmos inputs 2 0.65 x vdd ? v dd v v il(cmo s) low-level input voltage cmos inputs 2 0 ? 0.35 x vdd v v il (static) static low-level input voltage 3 ck, ck , - ? 0.35 x vdd v v ix(ac) differential input crosspoint voltage range(1.5v operation, ddr3-800/1066/1333/1600) ck, ck , fbin, fbin 0.5xv dd - 175 mv 0.5 x v dd 0.5xv dd + 175 mv v 0.5xv dd - 200 mv 4 0.5 x v dd 0.5xv dd + 200 mv 4 v differential input crosspoint vo ltage range(1.35v operation, ddr3l-800/1066/1333/1600) ck, ck , fbin, fbin 0.5xv dd - 150 mv 0.5 x v dd 0.5xv dd + 150 mv v 0.5xv dd - 180 mv 5 0.5 x v dd 0.5xv dd + 180 mv 5 v v id(ac) differential input voltage 6 (1.5v operation, ddr3-800/1066/1333) ck, ck 350 ? v dd mv differential input voltage 6 (1.5v operation, ddr3-1600) ck, ck 300 ? v dd mv differential input voltage 6 (1.35v operation, ddr3-800/1066/1333) ck, ck 300 ? v dd mv differential input voltage 6 (1.35v operation, ddr3-1600) ck, ck 270 ? v dd mv i oh high-level output current 7 all outputs except errout -11 ? ? ma i ol low-level output current 7 all outputs except errout 11 ? ?- ma
1.35v/1.5v registering clock driver with parity test and quad chip select 23 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature voltage waveforms; input clock v ix ( ac ) = 0.5 x v dd 175 mv (1.5v operation) or 0.5xv dd 150 mv (1.35 v operation) i ol low-level output current errout 25 ? ? ma v od differential re-driven clock sw ing (1.5v op eration) yn, yn 500 ? v dd mv differential re-driven clock swing (1.35v operation) yn, yn 450 ? v dd mv v ox differential output crosspoint voltage (1.5v operation) yn, yn 0.5xv dd ? 100 mv ? 0.5xv dd + 100 mv v differential output crosspoint voltage (1.35v operation) yn, yn 0.5xv dd ? 90 mv ? 0.5xv dd + 90 mv v ddr3-800 ddr3-1066 ddr3-133 3 ddr3-1600 t case (max) case temperature 8 109 9 108 9 106 9 103 9 o c 1 dcke0/1, dodt0/1, da0 ..da15, dba0..dba2, dras , dcas , dwe , par_in, dcs[1:0] when qcsen = high, dcs[3:0] when qcsen = low. 2 reset , mirror 3 this spec applies on ly when both ck and ck are actively driven low. it does not apply when ck/ck are floating. 4 extended range for vix is only allowed for clock (ck and ck ) and if single-ended clock input signals ck and ck are monotonic with a single-ended swing vsel / vseh of at least vdd/2 +/-275 mv, and when the differential slew rate of ck - ck is larger than 4 v/ns. 5 extended range for vix is only allowed for clock (ck and ck ) and if single-ended clock input signals ck and ck are monotonic with a single-ended swing vsel / vseh of at least vdd/2 +/-243 mv, and when the differential slew rate of ck - ck is larger than 3.6 v/ns 6 vid is the magnitude of the difference between the input level on ck and the input level on ck see diagram (voltage waveforms; input clock) 7 default settings 8 measurement procedure jesd51-2 9 this spec is meant to guarantee a tj of 125c by the sste32882 device. since tj cannot be measured or observed by users, tcase is specified instead. under all thermal condition, the tj of a sste3 2882 device shall not be higher than 125 o c. symbol parameter signals min nom max unit v ix ( ac ) v ix ( ac ) v id
1.35v/1.5v registering clock driver with parity test and quad chip select 24 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature dc current specifications operating electrical characteristics symbol parameter 1 1 the reset and mirror inputs of the device must be held at valid voltage levels (not floating) to ensure proper device operation. the differential inputs must not be floating unless reset is low. conditions min typ 2 2 all typical values are at v dd = 1.5v, t a = 25c. max unit i i input current reset , mirror, v i =v dd or gnd 5 ? a qcsen input current qcsen , v i =v dd or gnd -150 5 i id input current data inputs 3 , v i =v dd or gnd 3 dcken, dodtn, dan, dban, dras , dcas , dwe , dcsn, par_in are measured while reset is pulled low. 5 ? a ck, ck 4 ; v i =v dd or gnd 4 the ck and ck inputs have pull-down resi stors in the range of 10k ? to 100k ? . -5 150 ? a i oh high-level output current qn 5 5 qn = qxan, qxcsn , qxcken, qxodtn, qxras , qxcas , qxwe , and qxban. -11 ma yn, yn , fbout, fbout -11 ma i ol low-level output current qn 5 11 ma yn, yn , fbout, fbout 11 ma errout 25 ma i dd 6 6 the supply current is measured as the total current consumption on the av dd , pv dd , and v dd supply current pins. io = 0. static standby current reset = gnd and ck = ck = v il ( ac )5ma low-power static operating reset =v dd and ck = ck = v il ( ac ), mirror = v dd , dcs [1:0] = [0,1] 15 ma i ccd dynamic operating -- input clock only; active outputs reset =v dd , mirror = v dd , v i = v ih ( ac ) or v il ( ac ), rc0[dba0]=0, rc0[dba1]=0, ck and ck switching 50% duty cycle, i o = 0, dcs0 = l, dcs1 = h. v dd = v ddmax 68 ? a/mhz dynamic operating -- per each data input reset =v dd , mirror = v dd , v i = v ih ( ac ) or v il ( ac ), ck and ck switching 50% duty cycle. one data input switching at one half clock frequency, 50% duty cycle; rc0[dba0]=0, rc0[dba1]=0, i o = 0, dcs0 = l, dcs1 = h. v dd = v ddmax 16 ? a/clock mhz/ d input
1.35v/1.5v registering clock driver with parity test and quad chip select 25 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature capacitance values symbol parameter conditions min typ max unit c i input capacitance, data inputs see footnote 1 1 this parameter is not subject to produc tion test. it is verified by design and characterization. input capacitance is measure d according to jep147 ("procedure for measuring input capacitance using a vector network analyzer (vna)") with vdd, vss, avdd, avss, pvdd, pvss, v ref applied and all other pins (except the pi n under test) floating. input capacitance are measured with the device default settings when mirror=low. 1.5 - 2.5 pf input capacitance, ck, ck , fbin, fbin see footnote 1 2-3pf input capacitance, ck, ck , fbin, fbin (1.35 v operation) see footnote 1 1.5 - 2.5 pf c o output capacitance, re-driven and clock outputs qxa0..qxa15, qxba0..qxba2, qxcs0/1 , qxcke0/1, qxodt0/1, qxras , qxcas , qxwe , y0, y0 .. y3, y3 1-2pf c i ? delta capacitance over all inputs --0.5pf c ir input capacitance, reset , mirror, qcsen v i =v dd or gnd; v dd = 1.5 v --3pf
1.35v/1.5v registering clock driver with parity test and quad chip select 26 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature timing requirements symbol parameter conditions ddr3-800/ 1066/1333 ddr3-1600 unit min max min max f clock input clock frequency application frequency 1 1 all specified timing parameters apply. 300 670 300 810 mhz f test input clock frequency test frequency 2 2 timing parameters specified for frequency band 2 apply. 70 300 70 300 mhz t ch /t cl pulse duration, ck, ck high or low 0.4 0.4 t ck 3 3 clock cycle time. t act inputs active time before reset is taken high 4 4 this parameter is not necessarily production tested (see figure below). dcke0/1 = low and dcs[n:0] = high 88 t ck 3 t mrd command word to command word programming delay number of clock cycles between two command programming accesses 88 t ck 3 t indis input buffers disable time after dcke[1:0] is low dcke[1:0] = low; reset = high; ck/ck = toggling; rc9[dba1] = 1 and rc9[dba0] = 0 or 1 1 414 t ck 3 t qdis output buffers hi-z after qxcken is driven low dcke[1:0] = low; reset = high; ck/ck = toggling; rc9[dba1] = 1 and rc9[dba0] = 0 or 1 1.5 1.5 1.5 1.5 t ck 3 t ckoff number of tck required for both dcke0 and dcke1 to remain low before both ck/ck are driven low dcke[1:0] = low; reset = high; ck/ck = toggling 55 t ck 3 t ckev input buffers (dcke0 and dcke1) disable time after ck/ck = low dcke[1:0] = low; reset = high; ck/ck = low 22 t ck 3 tfixedoutputs static register output after dcke0 or dcke1 is high at the input (exit from power saving state) rc9[dba1] = 1 and rc9[dba0] = 0 or 1 1 314 t ck 3 t su setup time 5 5 setup (t su ) nominal slew rate for a rising signal is define d as the slew rate between the last crossing of v ref ( dc ) and first crossing of v ih ( ac ) min. setup (t su ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref ( dc ) and the first crossing of v il ( ac ) max. if the actual signal is always ear lier than the nominal slew rate line between shaded ?v ref ( dc ) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref ( dc ) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value . input valid before ck/ck 100 50 ps t h hold time 6 input to remain valid after ck/ck 175 125 ps
1.35v/1.5v registering clock driver with parity test and quad chip select 27 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature 6 hold (t h ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il ( dc ) max and the first crossing of v ref ( dc ). hold (t h ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih ( dc ) min and the first crossing of v ref ( dc ). if the actual signal is always late r than the nominal slew rate line between shaded ?dc level to v ref ( dc ) region? use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref ( dc ) region?, the slew rate of a tangen t line to the actual signal from the dc level to v ref ( dc ) level is used for derating value.
1.35v/1.5v registering clock driver with parity test and quad chip select 28 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature voltage waveforms for setup and hold times?hold time calculation v ss hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref ( dc ) - v il ( dc ) max ? tr = v ih ( dc ) min - v ref ( dc ) ? tf = v ddq v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region ck ck t su t h t su t h
1.35v/1.5v registering clock driver with parity test and quad chip select 29 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature voltage waveforms for setup and ho ld times?setup time calculation v ss setup slew rate setup slew rate rising signal falling signal ? tr ? tf v ref(dc) - v il(ac) max ? tf = v ih(ac) min - v ref(dc) ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate v ref to ac region ck ck t su t h t su t h v ref to ac region
1.35v/1.5v registering clock driver with parity test and quad chip select 30 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ac specifications - out put timing requirements propagation delay timing 1 ck and yn left out for better visibility. 2 rca0 is re-driven command address signal based on input ca0. symbol parameter 1 1 see ?qn and yn load circuit? diagram. conditions ddr3-800/ 1066/1333 ddr3-1600 unit min max min max t pdm propagation delay, single-bit switching (1.5v operation) ck ? ck to output 2 2 see ?propagation delay timing? diagram below. 3t pdm range (t pdm_max - t pdm_min ) must remain as 350 ps. for example, if t pdm_min for a device is 0.65 ns, it?s t pdm_max cannot be more than 1.0 ns, if t pdm_max for a device is 1.2 ns, it?s t pdm_min cannot be less than 0.85 ns. 4 see ?voltage waveforms address floating? diagram. 0.65 1.0 0.65 1.0 ns propagation delay, single-bit switching (1.35v operation) 3 ck ? ck to output 2 0.65 1.2 0.65 1.2 t dis output disable time (1/2-clock pre-launch) yn/yn (falling edge) to output float 4 0.5+ tqsk1(min) 0.5+ tqsk1(min) ps output disable time (3/4-clock pre-launch) 0.25+ tqsk2(min) 0.25+ tqsk2(min) t en output enable time (1/2-clock pre-launch) yn/yn (falling edge) output driving 0.5- tqsk1(max) 0.5- tqsk1(max) ps output enable time (3/4-clock pre-launch) 0.75- tqsk2(max) 0.75- tqsk2(max) ck (1) dcs c/a qxcsx qn(c/a) qn(c/a) input standard c/a yn (1) qxckex, qxodtx qxcsx , qxckex, qxodtx n n+1 n+2 n+3 n+4 n+5 n+6 pre- launch ca0 3/4 clock qn(c/a) pre-launch time rca0 (2) rca0 yn (1) t pdm
1.35v/1.5v registering clock driver with parity test and quad chip select 31 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature output buffer characteri stics - edge rates over specifie d operating free-a ir temperature range symbol parameter conditions ddr3ddr3l- 800/1066/1333 ddr3/ddr3l- 1600 unit min max min max dv/dt_r rising edge slew rate 1 (1.5v operation) 1 measured into test load at default register setting. 272.05.5 v/ns rising edge slew rate 1 (1.35v operation) 1.8 5.0 1.8 5.0 dv/dt_f falling edge slew rate 1 (1.5v operation) 272.05.5 v/ns falling edge slew rate 1 (1.35v operation) 1.8 5.0 1.8 5.0 dv/dt_d 2 2 difference between dv/dt_r (rising ed ge rate) and dv/dt_f (falling edge rate). absolute difference between dv/dt_r and dv/dt_f 1 ? 1 ? 1v/ns
1.35v/1.5v registering clock driver with parity test and quad chip select 32 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature clock driver characterist ics at application fre quency (frequency band 1) symbol parameter conditions ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit min max min max min max min max t jit ( cc +) cycle-to-cycle period jitter 0 40 0 40 0 40 0 30 ps t jit ( cc -) cycle-to-cycle period jitter -40 0 -40 0 -40 0 -30 0 ps t stab stabilization time - 6 - 6 - 6 - 6 s t fdyn dynamic phase offset -50 50 -50 50 -50 50 -40 40 ps t cksk fractional clock output skew 1 - 15 - 15 - 15 - 10 ps t jit ( per ) yn clock period jitter -40 40 -40 40 -40 40 -30 30 ps t jit ( hper ) half period jitter -50 50 -50 50 -50 50 -40 40 ps t pwh/pwl yn pulse width hig/low duration 3 t pw = 1/2t ck - i t jit (hper)min i to 1/2t ck - i t jit (hper)max i 1.200 1.300 0.888 0.988 0.700 0.800 0.585 0.665 ns t qsk 1 2 qn output to yn clock tolerance (standard 1/2-clock pre-launch) output inversion enabled -100 200 -100 200 -100 200 -100 100 ps output inversion disabled -100 300 -100 300 -100 300 -100 200 t qsk 2 4 qn output to yn clock tolerance (3/4 clock pre-launch) output inversion enabled -100 200 -100 200 -100 200 -100 100 ps output inversion disabled -100 300 -100 300 -100 300 -100 200 t staoff average delay through the register beween the input clock and output clock over ?n? cycles 5 . (1.5v operation) standard 1/2-clock pre-launch t staoff = t pdm + 1/2 t ck 1.9 2.251.591.941.401.75 1.28 1.63 ns 3/4 clock pre-launch t staoff = t pdm + 3/4 t ck 2.53 2.88 2.06 2.41 1.77 2.12 1.59 1.94 ns average delay through the register beween the input clock and output clock 5 . (1.35v operation) standard 1/2-clock pre-launch t staoff = t pdm + 1/2 t ck 1.90 2.45 1.59 2.14 1.40 1.95 1.28 1.63 ns 3/4 clock pre-launch t staoff = t pdm + 3/4 t ck 2.53 3.08 2.06 2.61 1.77 2.32 1.59 1.94 t dynoff 6 maximum variation in delay between the input & output clock - 160 - 130 - 110 - 90 ps
1.35v/1.5v registering clock driver with parity test and quad chip select 33 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature 1. this skew represents the absolute output clock skew and contains the pad skew and pa ckage skew (see ?clock output (yn) skew? ). this parameter is specified for the clock pairs on ea ch side of the register independently. the skew is applicable to left side clo ck pairs between y0/y0 and y2/y2 , as well as right side of the clock pairs between y1/y1 and y3/y3 . this is not a tested parame ter and has to be considered as a design goal only. 2. this skew represents the absolute qn skew compared to the output clock (yn), and c ontains the register pad skew, clock skew and package routing skew (see ?qn output skew for standard 1/2-clock pre-la unch?). the output cl ock jitter is not incl uded in this skew. the qn output can either be early or late. this parameter applies to each si de of the register independe ntly. the parameter includes the skew related to simultaneous sw itching noise (sso). 3. the parameter is a measure of the output clock pulse width high/low. the output cl ock duty cycle can be calculated based on t pw . 4. this skew represents the absolute qn skew compared to the output clock (yn), and c ontains the register pad skew, clock skew and package routing skew (see ?qn output skew for standard 3/4-clock pre-la unch?). the output cl ock jitter is not incl uded in this skew. the qn output can either be early or late. this parameter applies to each si de of the register independe ntly. the parameter includes the skew related to simultaneous sw itching noise (sso). 5. this parameter measures th e delay from the rising different ial input clock which samples in coming c/a to the rising differen tial output clock that will be used to sample the same c/a data. t staoff may vary by the amount of t dynoff based on voltage and temperature drift as well as tracking error and jitte r. including this variation t staoff may not exceed the limits set by t staoff(min) and t staoff(max). 6. see ?measurement requirement for t staoff and t dynoff ?. 7. implies a -3 db bandwidth and jitter peaking of 3 db. clock output (yn) skew ssc modulation frequency 30 33 30 33 30 30 33 khz ssc clock input frequency deviation 0.00 -0.5 0.00 -0.5 0.00 -0.5 0.00 -0.5 % t band pll loop bandwidth (-3 db from unity gain) 25 7 30 7 35 7 40 7 -mhz symbol parameter conditions ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit t ck t cksk t cksk y0 y0 y2 y2 y2 y2
1.35v/1.5v registering clock driver with parity test and quad chip select 34 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature qn output skew for standard 1/2-clock pre-launch qn output skew for 3/4-clock pre-launch yn yn tck tck/2 t qsk1 max tck/2 qn(c/a) ideal qn(c/a) late qn(c/a) early t qsk1 min yn yn tck qn(c/a) ideal qn(c/a) late t qsk2 max tck/4 3/4*tck qn(c/a) early t qsk2 min
1.35v/1.5v registering clock driver with parity test and quad chip select 35 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature clock driver characteristics at te st frequency (frequency band 2) symbol parameter conditions min. max. unit t jit ( cc ) cycle-to-cycle period jitter 0 160 ps t stab stabilization time ? 15 us t cksk total clock output skew 1 1 this skew represents the absolu te output clock skew and contains the pad skew and package skew. 100 ps fractional clock output skew 2 2 this skew represents the absolute out put clock skew and contains the pad skew and package skew (see ?clock output (yn) skew?). this parameter is specified for the clock pairs on each side of the register in dependently. the skew is applicable to t he left side of the clock pair between y0/y0 and y2/y2 , as well as the right side of the clock pair between y1/y1 and y3/y3 . tbd t jit ( per ) yn clock period jitter -160 160 ps t jit ( hper ) half period jitter -200 200 ps t qsk 1 3 3 this skew represents the abso lute qn skew compared to the output clock yn, and contains the register pad skew, clock skew, and package routing skew (see ?q n output skew for standard 1/2 clock pre-laun ch?). the output clock jitter is not included in this skew. this parameter applies to each side of the register independently. the qn output can either be early or late. qn output to clock tolerance (standard 1/2-clock pre-launch) output inversion enabled -100 tbd ps t qsk 1 sso 4 4 this skew represents the abso lute qn skew compared to the output clock yn, and contains the register pad skew, clock skew, and package routing skew. the output clock jitter is not included in this skew. this parameter applies to each side of the reg ister independently. this parameter includes the skew related to simultaneous switching no ise (sso). the qn output can either be early or late. output inversion disabled -100 tbd t qsk 2 5 5 this skew represents the abso lute qn skew compared to the output clock yn, and contains the register pad skew, clock skew, and package routing skew (see ?q n output skew for standard 3/4 clock pre-laun ch?). the output clock jitter is not included in this skew. this parameter applies to each side of the register independently. the qn output can either be early or late. output clock tolerance (3/4 clock pre-launch) output inversion enabled -100 tbd ps t qsk 2 sso 6 6 this skew represents the abso lute qn skew compared to the output clock yn, and contains the register pad skew, clock skew, and package routing skew. the output clock jitter is not included in this skew. this parameter applies to each side of the reg ister independently. this parameter includes the skew related to simultaneous switching no ise (sso). the qn output can either be early or late. output inversion disabled -100 tbd t dynoff maximum re-driven dynamic clock offset 7 7 the re-driven clock signal is ideally cen tered in the address/control signal eye. this parameter describes the dynamic devia tion from this ideal pos ition including jitter and dynamic phase offset. -500 500 ps
1.35v/1.5v registering clock driver with parity test and quad chip select 36 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature initialization the sste32882hlb can be powered-on at 1.5v or 1.35v. after the voltage transition, stable power is provided for a minimum of 200 s with reset asserted. when the reset input (reset ) is low, all input receivers are disabl ed, and can be left floating. the reset input is referenced to v dd /2, therefore the reference voltage (v ref ) is not required to be stable durin g reset. in addition, when reset is low, all control registers are restored to their default states. the qacke0, qacke1, qbcke0 and qbcke1 ou tputs must drive low during reset, and all other outputs must float. as long as the reset input is pulled low the register is in low power state and input termination is not present. a certain period of time (t act ) before the reset input is pulled high the reference voltage needs to be stable within specification, the clock input signal must be stable, the register inputs dcs[n:0] must be pulled high to prevent any fortuitous access to the control registers. also, dcke0 and dcke1 inputs must be pulled low for the complete stabilization time (t stab ). after reset and after the stabilization time (t stab ), the register must meet the input setup and hold specification before accepting and transfering data from the register inputs to the register outputs. the reset input must always be held at a valid logic level once the input clock is present. to ensure defined outputs from the register before a stable cloc k has been supplied, the register must enter the reset state du ring power-up. it may leave this state only after a low to high transition on reset while a stable clock signal is present on ck and ck . in the ddr3 rdimm application, reset is specified to be completely as ynchronous with resp ect to ck and ck . therefore, no timing relationship can be guaranteed betw een the two. when entering reset, the re gister will be cleared and the data output s will float quickly (except for qacke0, qacke1, qbcke0 and qbcke1, which are driven low), relative to the time to disable the differential input receivers. th e figure below shows the system timing of clock and data during the initialization sequence. timing of clock and data during initialization sequence 1 ck is left out for better visibility. 2 dcke0, dcke1, dodt0, dodt1, dcs0 and dcs1 are not included in this range. 3 n = 1 for quadcs disabled mode, n = 3 for quadcs enabled mode. 4 qxcken, qxodtn, qxcsn are not included in this range. ck (1) v dd dcke[0:1] reset da/c (2) dodt[0:1] dcs0 dcs[n:1] (4) pll lock 6 ? s t act = 8 cycles t init = 200 ? s controller guarantees high logic controller guarantees high logic controller guarantees valid logic controller guarantees low logic controller guarantees valid logic register proper function and timing starting from here register drives cke low until ready to transfer input signals qxcke[0:1] qxodt[0:1] qxcs[n:0] (4) errout step 0,1 step 2 step 3 step 5 step 6 step 7 step 4 qxa/c (3) high or low y[0:3] (1) register guarantees low logic register guarantees high logic
1.35v/1.5v registering clock driver with parity test and quad chip select 37 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature from a device perspective, the initiali zation sequence must be as shown in the following device initialization table. sste32882hlb device in itialization sequence 1 . 1. x=logic low or lolgic high. z=floating. 2. n = 1 for quadcs disabled mode , n = 3 for quadcs enabled mode. 3. the feedback clock (fbout and fbout ) pins may or may not be actively driven by the device. 4. the system may power up using either 1.5v or 1.35v. the bios reads the spd and adjusts the voltage if needed from 1.35v to 1 .5v or from 1.5v to 1.35v. after the voltage transition, stable power is provided for a minimum of 200 us with reset asserted. 5. qxcken and errout will be driven to these logic st ates by the register after reset is driven low and vdd is 1.5v or 1.35v (nominal). 6. this indicates the state of qxodtx after reset switches from low-to-high and befo re the rising ck edge (falling ck edge). after the first rising ck edge, within (t stab - t act ) us, the state of qxodtx is a function of dodtx (high or low). 7. step 7 is a typical usage exampl e and is not a register requirement. reset initialization with stable power the timing diagram in the following diagram depicts the initialization sequence with stable power and clock. this will apply to the situation when we have a soft reset in the system. reset will be asserted for minimum 100ns. this reset timing is based on ddr3 dram reset initialization with stable power requ irement, and is a minimum requirement. actual reset timing can vary base on specific system requirement, but it cannot be less than 100ns as required by jesd79-3 specification. step power inputs: signals provided by the controller outputs: signals provided by the device vdd, avdd, pvdd reset vref dcs [n:0] 2 dodt [0:1] dcke [0:1] da/c par_in ck,ck qcs [n:0] 2 qodt [0:1] qcke [0:1] qxa/c errout y[0:3] y [0:3] fb out 3 00vx or zx or z x or z x or z x or z x or z x or z x or z z z z z z z z 1 0-->v dd x or z x or z x or z x or z x or z x or z x or z l x or z x or z x or z x or z x or z x or z x or z 2 4 v dd 1.5v-->1.35v 1.35v-->1.5v lx or z x or z x or z x or z x or z x or z l z z l 5 z h 5 zz 3 v dd lx or z x or z x or z x or z x or z x or z running zz lz hzz 4 v dd lx or zhx or zl x or z x or z running z z lz hzz 5 v dd l stable voltage hx l xx running z z lz hzz 6 v dd h stable voltage hx l xx running h l 6 lx h running running 7 7 v dd h stable voltage h x x x x running after step 6 (step 7 and beyond), the de vice outputs are as defined in the device function tables.
1.35v/1.5v registering clock driver with parity test and quad chip select 38 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature timing of clock and data during initialization sequence with stable power 1 ck is left out for better visibility. 2 dcke0, dcke1, dodt0, dodt1, dcs0 and dcs1 are not included in this range. 3 qxcken, qxodtn, qxcsn are not included in this range. 4 n = 1 for quadcs disabled mode, n = 3 for quadcs enabled mode. ck (1) v dd dcke[0:1] reset da/c (2) dodt[0:1] dcs0 dcs [n:1] pll lock 6 ? s t act = 8 cycles t init_power_stable = 100 ns controller guarantees high logic controller guarantees high logic controller guarantees low logic controller guarantees valid logic register proper function and timing starting from here register drives cke low until ready to transfer input signals qxcke[0:1] qxcs [0:1] errout step 0,1 step 2 step 3 step 5 step 6 step 7 register guarantees high logic step 4 register guarantees low logic h or l h or l hi-z y[0:3] (1) qxa/c (3) controller guarantees valid logic h or l h or l qxodt[0:1] hi-z h or l h or l h or l h or l high or low
1.35v/1.5v registering clock driver with parity test and quad chip select 39 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature sste32882hlb device in itialization sequence 1 when power and clock are stable 1. x=logic low or lolgic high. z=floating. 2. n = 1 for quadcs disabled mode , n = 3 for quadcs enabled mode. 3. the feedback clock (fbout and fbout ) pins may or may not be actively driven by the device. 4. qxcken and errout will be driven to these logic st ates by the register after reset is driven low and vdd is 1.35v or 1.5v (nominal). 5. this indicates the state of qxodtx after reset switches from low-to-high and befo re the rising ck edge (falling ck edge). after the first rising ck edge, within (t stab - t act ) us, the state of qxodtx is a function of dodtx (high or low) parity the sste32882hlb includes a parity checking function. the sste32882hlb accepts a parity bit from the memory controller at its input pin par_in one cy cle after the corresponding data input, comp ares it with the data received on the d-inputs and indicates on its open-drain errout pin (active low) whether a parity er ror has occurred. the computation only takes place for data which is qualifie d by at least one of the dcs[n:0] signals being low. if an error occurs, and errout is driven low with the third input clock edge after the corresponding data on the d-inputs. it becomes high impedance with the 5th input clock cycle after the da ta corresponding with a parity error. in case of consecutive errors errout becomes high impedance with the 5th input clock cycle af ter the last data corresponding with a parity error. the dimm-dependent signal s (dcke0, dcke1, dcs0 , dcs1 , dodt0 and dodt1) are not in cluded in the parity check computations. parity timing scheme waveforms the par_in signal arrives one input clock cycle after the corresponding data input signals. errout is generated three input clock cycles after the corresponding data is registered. if errout goes low, it stays low for a minimum of two input clock cycles or until reset is driven low. the following figure shows the parity diagram with single parity-error occurrence and assumes the occurrence of only one parity er ror when data is clocked in at the n input clock cycle (par_in clocked in on the n+1 input clock cycle). step power inputs: signals provided by the controller outputs: signals provided by the device vdd, avdd, pvdd reset vref dcs [n:1] 2 dodt [0:1] dcke [0:1] da/c par_i n ck, ck qcs [0:1] qodt [0:1] qcke [0:1] qxa/c errout y[0:3] y [0:3] fb out 3 0 v dd h stable voltage x x x x x running x x x x x running running 1 v dd h stable voltage x x x x x running x x x x x running running 2 v dd l stable voltage x x x x x running z z l 4 z h 4 zz 3 v dd l stable voltage x x x x x running zz lz hzz 4 v dd l stable voltage h x l x x running z z lz hzz 5 v dd l stable voltage hx l xx running z z lz hzz 6 v dd h stable voltage hx l xx running h l 5 lx h running running 7 v dd h stable voltage h x x x x running after step 6 (step 7 and beyond), the device outputs are as defined in the device function tables.
1.35v/1.5v registering clock driver with parity test and quad chip select 40 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature timing of clock, data and parity signals 1 ck left out for better visibility. the next figure shows the parity diagram with two consecutive parity-error occurren ces and assumes the occurrence of both parity errors when data is clocked in at the n and n+1 input clock cycles (par_in clocked in on the n+1 and n+2 input clock cycles). two consecutive parity-error occurrences 1 ck left out for better visibility. the next figure shows the parity diagram with two parity-err or occurrences separated by a clock cycle w ith no error occurrence. the diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+2 input clock cycles (par_in clocked in on the n+1 and n+3 input clock cycles). two parity-error occurrences separated by a clock cycle of no error occurrence 1 ck left out for better visibility. the next figure shows the parity diagram with two parity-error occurrences separated by two inpu t clock cycles with no error occurrence. the diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+3 input clock cycles (par_in clocked in on the n+1 and n+4 input clock cycles). ck (1) ca input par_in ca0 p0 ca1 p1 ca2 p2 errout n n+1 n+2 n+3 n+4 n+5 n+6 errout resulting from ca0 - p0 ck (1) ca input par_in ca0 p0 ca1 p1 ca2 p2 errout n n+1 n+2 n+3 n+4 n+5 n+6 errout resulting from ca0 - p0, followed by 2nd error in ca1 - ck (1) ca input par_in ca0 p0 ca1 p1 ca2 p2 errout n n+1 n+2 n+3 n+4 n+5 n+6 errout resulting from ca0 - p0, followed by 2nd error in ca2 - p2 n+7 n+8 n+9 ca3 p3 p4 ca4 ca5 p5
1.35v/1.5v registering clock driver with parity test and quad chip select 41 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature two parity-error occurrences separated by two clock cycles of no error occurrence 1 ck left out for better visibility. the next figure shows the parity diagram with two parity-error occurrences; during chip-select and chip-deselect modes. the diagram assumes the occurrence of both par ity errors when data is clocked in at the n and n+1 input clock cycles (par_in clocked in on the n+1 and n+2 input clock cycles). parity erro r in the chip-select mod is det ected, but parity error in the chip-deselect mode is ignored. parity-error occurrence in chip-deselect mode 1 ck left out for better visibility. the next figure shows the parity diagram with two parity-e rror occurrences; during normal operation and during control register programming. the diagra m assumes the occurrence of both parity errors wh en data is clocked in at the n and n+3 input clock cycles (par_in clocked in on the n+1 and n+4 input clock cycles). the data on the n+3 input clock pulse is intended for the control mode register. parity error during control mode regi ster programming is detected and the parity functionality is t he same as during normal operation. if a pa rity error occurs, the command is ignored. ck (1) ca input par_in ca0 p0 ca1 p1 ca2 p2 errout n n+1 n+2 n+3 n+4 n+5 n+6 errout resulting from ca0 - p0, followed by 2nd error in ca3 - p3 n+7 n+8 n+9 ca3 p3 p4 ca4 ca5 p5 ck (1) ca input par_in ca0 p0 ca1 p1 ca2 p2 errout n n+1 n+2 n+3 n+4 n+5 n+6 errout resulting from ca0 - p0, subsequent parity errors during dcsx high ignored dcsx
1.35v/1.5v registering clock driver with parity test and quad chip select 42 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature parity-error occurrences duri ng control word programming 1 ck left out for better visibility. power saving modes the device supports different power saving mechanisms. when both inputs ck and ck are being held low the device stops operation and enters low-power static and standby operation. it stops its pll and floats all outputs except qacke0, qacke 1, qbcke0 and qbcke1 which are kept driven low. before the device is taken out of standby operation by applying a stable input clock signal, the register inputs dcs[n:0] must be pulled high to prevent accidential access to the control registers and dcke0 as well as dcke1 must be pulled low for a certain period of time (t act ). the input clock must be stable for a time (t stab ) before any access to the device takes place. stopping the clocks (ck = ck = low) will only put the sste32882hlb in low-power mode and will not clear the content of the control words. the control words will reset only when reset is diven low. a float feature can be enabled by setting the corresponding bit in the control register. this causes the device to monitor all the dcs[n:0] inputs and to float all outputs corresponding with the chip select gated inputs when all the dcs[n:0] inputs are high. if any one of the dcs[n:0] inputs are low, the qn outputs will function normally. once all the dcs[n;0] inputs are high, the gated address command inputs to th e register can float to co nserve input termination power. dcke0, dcke1, dodt0 and dodt1 need to be driven by the system all the time. the reset input has priority over all other power saving mechanisms. when reset is driven low, it will force the qn outputs to float, the errout output high, the qacke0, qacke1, qbcke0 and qbcke1 outputs low, and disables input bus termination (ibt). register cke power down if rc9[dba1] is set to ?1?, the sste32882hlb monitors both dcken input signals and enters into power saving state when it latches low on both dcken inputs and at least one of the dc ken input has transitioned from high to low. if any input chip select signal (dcs[n:0] ) is asserted together with dcken, the sste3 2882hlb transfers the corresponding command to its outputs together with qxcken low. there are two modes of cke power down se lected by rc9. bit dba0 in rc9 indicates whether the register turns off ibt or keeps ibt on. ck (1) ca input par_in ca0 p0 ca1 p1 ca2 p2 errout n n+1 n+2 n+3 n+4 n+5 n+6 errout resulting from ca0 - p0, followed by 2nd e rror during control word access in ca3 - p3 n+7 n+8 n+9 ca3 p3 p4 ca4 ca5 p5 dcs0 dcs1
1.35v/1.5v registering clock driver with parity test and quad chip select 43 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature register cke power down with ibt off upon entry into cke power down mode with ibt off, all regi ster input buffers including ib t are disabled except for ck/ck , dcken, fbin/fbin , and reset . the sste32882hlb disables input buffers within tindis clocks after latching both dcken low. in order to eliminate and fals e parity check error, the par_in input buff er has to be kept active for 1 tck after address and command input buffers disabled. after tindis, the register can tolerate floating input except for ck/ck , dcken and reset . the sste32882hlb also disables a ll its output buffers except for yn/yn , qxodtn, qxcken and fbout/fbout . the yn/yn and fbout/fbout outputs continue to drive a valid phase accurate clock signal. the qxodtn and qxcken outputs are driven low. the register output buffers are hi-z t qdis clock after qxcken is driven low. this is shown in the next figure. power down mode entry and exit with ibt off (1) i, j only apply for quadcs capable regist er. when quadcs is enabled, i = 2, j = 3. (2) quadcs disabled: during cke power down entry/exit, driving dcs[1,0] low is illegal as it will force sste32882 into register control word access mode. (3)upon cke power down exit, qxcsn will be held high for maximum of 1 tck regardless of what dcsn input level is. for all other operation qxcsn outputs will follow dcsn inputs. h or l ck reset dan,dban dras , dodtn dcken dcas , dwe high or low high or low low high tindis high or low high hi-z high yn qxan, qxodtn high or low low high high or low high hi-z qxras , qxcas , qxwe qxcken high or low low low hi-z hi-z tfixedoutput hi-z hi-z hi-z t qdis output buffers are hi-z n n-1 n+4 n+8 n+12 n+16 n+20 n n-1 n+4 n+8 n+12 n+16 n+20 qxban high or low high hi-z high low high high hi-z high or low low high or low high or low par_in hi-z qxcs[i,0] qxcs[j,1] dcs[i,0] dcs[j,1] h or l either or both dcken inputs are driven high either or both qxcken outputs are driven high t en see note 3 see note 3
1.35v/1.5v registering clock driver with parity test and quad chip select 44 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature to re-enable the register from this power saving state, valid logi c levels are required at all regi ster inputs when either or b oth dcken inputs are driven high. upon either dcke0 or dcke1 in put going high, the register immediately starts driving high on the appropriate qxck en signal. the qxcsn signals are driven high and qxodtn si gnals are driven low. other output signals qxras , qxcas , qxwe , and qxaddr are driven either high or low to en sure stable valid logic an all register outputs when qxcken goes high. the register drives output signals to these levels for t fixedoutput to allow input receivers to be stabilized. after the input reci evers are stabilized, the regist er output follow their corres ponding input levels. when exiting cke power down mode, either one of the chip select register inputs dcsn can be asserted for 1 tck. for quadcs capable register, when working in quad rank mode, either two of the chip select register inputs dcsn can be asserted for 1 tck. the register guarantees th at input receivers ar e stabilized within t fixedoutput clocks after dcken input is driven high. this is shown in the previous diagram. register cke power down with ibt on upon entry into cke power down mode with ibt on, all regist er input buffers excluding ibt are disabled except for ck/ck , dcken, dodtn, fbin/fbin , and reset . the sste32882hlb disables input buffers within tindis clocks after latching both dcken low. in order to eliminate any false parity check er ror, the par_in input buffer has to be kept active for 1 tck after the address and command input buffers are disabled. afte r tindis, the register can tolerate floating input except for ck/ck , dcken, dodtn and reset . the sste32882hlb also disables all its output buffers except for yn/yn , qxodtn, qxcken and fbout/fbout . the yn/yn and fbout/fbout outputs continue to drive a va lid phase accurate clock signal. the qxcken outputs are driven low. th e register output buffers are hi-z t qdis clock after qxcken is driven low. this is shown below.
1.35v/1.5v registering clock driver with parity test and quad chip select 45 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature power down mode entry and exit with ibt on (1) i, j only apply for quadcs capable regist er. when quadcs is enabled, i = 2, j = 3. (2) quadcs disabled: during cke powe r down entry/exit, driving dcs[1,0] low is illegal as it will force sste32882 into register control word access mode. (3) upon cke power down exit, qxcsn will be held high for a maximum of 1 tck regardless of what dcsn input level is. for all other operation, qxcsn outputs will follow dcsn inputs. to re-enable the sste32882hlb from this power down mode with ibt on, valid logic levels are required at all device inputs when either or both dcken inputs are driven high. upon either dcke0 or dcke1 input going high, the sste32882hlb immediately starts driving high on the appropriate qxcken signals. the qxcsn signals are driven high and the qxodtn signals follow the inputs. other output signals qxras , qxcas , qxwe and qxaddr are driven eith er high or low to ensure stable valid logic on all device outputs when qxcken goes hi gh. the device drives output signals to these levels for t fixedoutput to allow input receivers to be stablized. after the input receivers are stablized, the register output follow their corresponding input levels. when exiting cke power down m ode, either one of the chip select register inputs dcsn can be asserted for 1 tck. for quadcs capable re gister, when working in quad rank mode, either two of the chip select register inputs dcsn can be asserted for 1 tck. the device guarantees that input receivers are stablized within t fixedoutput clocks after dcken input is driven high. this is shown in the previous diagram. ck reset dan,dban dras , dodtn dcken dcas , dwe high, low or toggling high or low low high tindis high hi-z high yn qxan, qxodtn follows input (high, low or toggling) low high high hi-z qxras , qxcas , qxwe qxcken high or low hi-z hi-z tfixedoutput hi-z hi-z t qdis output buffers are hi-z n n-1 n+4 n+8 n+12 n+16 n+20 n n-1 n+4 n+8 n+12 n+16 n+20 qxban dcs[j,1] high or low high hi-z high high follows input (high or low) hi-z high or low h or l h, l or hi-z h, l or hi-z h or l follows input (high or low) tfixedoutput high or low high or low high or low high or low h, l or hi-z h, l or hi-z high h or l par_in hi-z h, l or hi-z dcs[i,0] qxcs[j,1] qxcs[i,0] h, l or hi-z h or l either or both dcken inputs are driven high either or both qxcken outputs are driven high t en see note 3 see note 3
1.35v/1.5v registering clock driver with parity test and quad chip select 46 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature clock stopped power down mode to support s3 power management mode or any other operation that allows yn clocks to float, the sste32882hlb supports a clock stopped power down mode. when both inputs ck and ck are being held low, (v il(static) ) or float (will eventually settle at low because of the (10k-100k ohm) pulldown resistor in the ck/ck input buffer, the device stops operation and enters low-power static and standby operation. the correspondi ng timing are shown in ?clock stopped power down entry and exit with ibt on? and ?clock stopped power down entry and exit with ibt off?. the register device will stop its pll and floats all outputs except qacke0, qacke1, qbcke0 and qbcke1, which must be kept driven low. the clock stopped power down mode can only be utilized once the dram received a self refresh command. in this state, the dram ignores all inputs except cke. hence, all register outputs be sides qxcke0 and qxcke1 can be disabled. clock stopped power down mode entry to enter clock stopped power down mode, the register will first enter cke power down mode. once in cke power down mode, the host will deasserts dcken for a minimum of one tckoff before pulling ck and ck low. after holding ck and ck low (v il(static) ) for at least one tckev, both ck and ck can be floated (because of the (10k-100k ohm) pulldown resistor in the ck/ck input buffer, ck/ck will stay at low even though they are not being dr iven).the register is now in clock stopped power down mode. after ck and ck are pulled low, the host has to k eep dcken stable for at least one t ckev before it can float dcken. at this point, all input receivers and input termin ation of the sste32882hlb ar e disabled. the only active input circuits are ck and ck , which are required to detect the wake up request from the host. clock stopped power down mode exit to wake up the register after clock stopped power down, the host must drive the register inputs dcs[n:0] must be driven to high (to prevent accidental access to the co ntrol registers), and dcken to low. after that, the host can apply a frequency and phase accurate input clock signal. within t act after ck and ck resumed normal operation, the sste32882hlb outputs start becoming a function of their corresponding inputs. the state of the dcs[n:0] inputs must not be changed before the end of t stab . the input clock ck and ck must be stable for a time equal or greater than t stab before any access to the sste32882hlb can takes place.
1.35v/1.5v registering clock driver with parity test and quad chip select 47 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature clock stopped power down entry and exit with ibt on (1) i, j only apply for quadcs capable regist er. when quadcs is enabled, i = 2, j = 3. (2) with rc9 dba0=?0?. (3) when ck/ck inputs are floated, ck/ck inputs are pulled low by the (10k-100k ohm) pulldown resistor in the ck/ck input buffer. (4) upon cke power down exit, qxcsn will be held high for maximum of 1 tck regardless of what dcsn input level is. for all other operation qxcsn outputs will follow dcsn inputs. dan, dban input n-1 qxodtn n pp+4 qxcken dcs[j,1] output dodtn t stab mm+4 hi-z driven low hi-z hi-z qp+7 m+8 x x t ckoff t ckev t fixedoutput odt8 odt10 odt11 odt9 odt12 odt14 odt15 odt13 odt16 odt17 hi-z qxras , qxwe qxcas , n+4 tindis dras dcas dwe dcken high or low high or low dcs[i,0] high or low high or low h, l or hi-z h or l high, low or toggling high, low or toggling either or both dcken inputs are driven high hi-z hi-z hi-z hi-z hi-z low low tfixedoutput h, l or hi-z reset n n-1 yn qxan, qxban h or l high or low high or low follows input (high, low or toggling) follows input (high, low or toggling) n+4 either or both qxcken outputs are driven high qxcs[i,0] hi-z follows input (h or l) high or low qxcsn and qxodtn transfer from hi-z to high/low with in-accurate phase t qdis qxcs[j,1] follows input (h or l) high or low hi-z high par_in h, l or hi-z h, l or hi-z h, l or hi-z hi-z h, l or hi-z hi-z l or float* t en high high high high t act ck/ck high high high high see note 3 see note 3
1.35v/1.5v registering clock driver with parity test and quad chip select 48 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature clock stopped power down entry and exit with ibt off (1) i, j only apply for quadcs capable register. when quadcs is enabled, i = 2, j = 3. (2) with rc9 dba0=?1?. (3) when ck/ck inputs are floated, ck/ck inputs are pulled low by the (10k-100k ohm) pulldown resistor in the ck/ck input buffer. (4) upon cke power down exit, qxcsn will be held high for maximum of 1 tck regardless of what dcsn input level is. for all other operation qxcsn outputs will follow dcsn inputs. dan, dban input n-1 qxodtn n pp+4 qxcken dcs[j,1] output dodtn t stab mm+4 hi-z driven low hi-z hi-z qp+7 m+8 x x t ckoff t ckev t fixedoutput odt8 odt10 odt11 odt9 odt12 odt14 odt15 odt13 odt16 odt17 hi-z qxras , qxwe qxcas , n+4 tindis dras dcas dwe dcken low high or low dcs[i,0] high or low h or l high or low high or low either or both dcken inputs are driven high hi-z hi-z hi-z hi-z hi-z low low tfixedoutput reset n n-1 yn qxan, qxban h or l high or low high or low high or low n+4 either or both qxcken outputs are driven high qxcs[i,0 ] hi-z high or low qxcsn and qxodtn transfer from hi-z to high/low with in-accurate phase t qdis qxcs[j,1] high or low hi-z high high high or low high high low high pa r_in hi-z hi-z t en high high high high t act l or float* ck/ck see note 3 see note 3
1.35v/1.5v registering clock driver with parity test and quad chip select 49 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature dynamic 1t/3t timing transaction and output inversion enabling/disabling output inversion is always enabled by default, after reset is de-asserted, to conserve powe r and reduce simultaneous output switching current. all a-outputs will follow the equivalent inputs, however the following b-outputs will be driven to the complement of the matching a-outputs: qba3 - qba9, qba11, qba13 - qba15, qbba0 - qbba2. the output inversion feature is not us ed during dram mrs command access. wh en output inversion is disabled, all corresponding a and b output drivers of the sste32882hlb are dr iven to the same logic levels. output inversion must be disabled when the mrs and emrs commands must be issued to the drams, for example, to assure that the same programming is issued to all drams in a rank. with output inversion disabled during mrs access, in order to allow correct dram accesses with the consequently increased simultaneous switching propagation delay the devices supports 3t timing. if this f eature is invoked the device drives the received data on its outputs for thee cycles instead of one. the only excep tions are the qxcs[n:0] outputs, which are the qacs0 , qacs1 , qbcs0 , and qbcs1 outputs in the quadcs disabled mode and are qcs[3:0] in the quadcs enabled mode. when the device decodes the mrs command (dras =0, dcas =0, dwe =0 and only one dcsn =0), it will disable the output inversion function and pass the dram mrs command with an additional (one) clock delay on the appropriate qncsx signal to the dram. back-to-back mrs command via the sste32882hlb must have a minimum of three clock delays. the sste32882hlb will automatically enable output inversion if there is no dram mrs command three clocks after the previous mrs command. the inputs and outputs relationships for 1t timing and 3t timing are shown in the following three diagrams. output inversion functional diagram qaxxx output qbxxx output dxxx input mrs decoder register
1.35v/1.5v registering clock driver with parity test and quad chip select 50 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature 1t timing during normal operation 1 ck and yn left out for better visibility. 2 n = 1 for quadcs disabled, n = 3 for quadcs enabled. ck (1) dcke[1:0] da[15:0], dba[2:0] input outputs @ 1t n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 dodt[1:0] dras dcas , dwe dcs0 dcs[n:1] (2) yn (1) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 qcke[1:0] qaa[15:0], qaba[2:0], qodt[1:0] qras qcas , qwe qcs0 qcs[n:1] (2) qba12, qba10, qba[2:0] qba[15:13], qba11, qba[9:13], qbba[2:0]
1.35v/1.5v registering clock driver with parity test and quad chip select 51 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature 3t timing during dram mrs command 1 ck and yn left out for better visibility. 2 n = 1 for quadcs disabled, n = 3 for quadcs enabled. ck (1) dcke[1:0] da[15:0], dba[2:0] input outputs @ 3t n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 dodt[1:0] dras dcas , dwe dcs0 dcs[n:1] (2) yn (1) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 qcke[1:0] qodt[1:0] qras qcas , qwe qcs0 qcs[n:1] (2) output inversion disabled output inversion enabled qaa[15:0], qaba[2:0], qba12, qba10, qba[2:0] qba[15:13], qba11, qba[9:3], qbba[2:0]
1.35v/1.5v registering clock driver with parity test and quad chip select 52 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature 3t timing during mult iple dram mrs commands 1 ck and yn left out for better visibility. 2 n = 1 for quadcs disabled, n = 3 for quadcs enabled. ck (1) dcke[1:0] da[15:0], dba[2:0] input outputs @ 3t n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 dodt[1:0] dras dcas , dwe dcs0 dcs[n:1] (2) yn (1) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 qcke[1:0] qodt[1:0] qras qcas , qwe qcs0 qcs[n:1] (2) output inversion disabled output inversion enabled qaa[15:0], qaba[2:0], qba12, qba10, qba[2:0] qba[15:13], qba11, qba[9:3], qbba[2:0]
1.35v/1.5v registering clock driver with parity test and quad chip select 53 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature control words the sste32882hlb registers have internal co ntrol bits for adapting the configuration of certain device features. the control bits are accessed by the simultaneous assertion of both dcs0 and dcs1 in the quadcs disabled mo de. in the quadcs enabled mode, the simultaneous assertion of both dcs2 and dcs3 during normal operation, and the assertion of all four dcs[3:0] inputs also results in cont rol word access. however, as sertion of any three dcs[3:0] inputs is not legal. register qn outputs including qxcke0, qxcke1, qxodt0 and qxodt1 remain in their previous state. select signals qxcs[n:0] are set to high during control word access. the sste32882hlb allocates decoding for up to 16 words of co ntrol bits, rc0 through rc15. selection of each word of control bits is presented on inputs da0 through da2 and dba2. data to be written into the configuration registers need to be presented on da3, da4, dba0 and dba1. bits da[15:5] need to be low, and at least one dcken input must be high, for valid data access. if power down mode is enabled in rc9[dba1] , at least one dcke must be high for valid control word access. the inputs on dras , dcas , dwe , and dodt[1:0] can be either high or low, and are ignored by the sste32882hlb during control word access. in all cases address and command parity is checked during cont rol word write operations. errout is asserted and the command is ignored if a parity error is detected. using this mech anism, controllers may use the sste32882hlb to validate the address and command bus signal inte grity to the module as long as one or more of the parity checked input signals da3-da15, dba0, dba1, dras , dcas , dwe are kept high. control word access must be possible at any defined frequency in dependent of the current settin g of dba1 control registers.
1.35v/1.5v registering clock driver with parity test and quad chip select 54 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature control words the device features a set of co ntrol words, which allow the optimization of th e device properties for different raw card design s. the different control words and settings are described below. a ny change to these control word s requires some time for the device to settle. for changes to the control word setting, ex cept for rc2 (bits dba1 and da3) and rc10, the controller needs to wait t mrd after the last control word access, before further access to the dram can take place. for any changes to the clock timing (rc2: bits dba1 and da3) and rc 10, this settling may take up to t stab time. all chip select inputs (dcs[n:0] ) must be kept high during that ti me. the control words can be accessed and wri tten to when running wi thin any one defined frequency band. control word decoding the values to be programmed into each control word are pr esented on signals da3, da4, dba0 and dba1 simultaneously with the assertion of the control word access through dcs0 and dcs1 , or dcs2 and dcs3 in the quadcs enabled mode, and the address of the control word on da0, da1, da2 and dba2. the reset default state of control words 0 .. 5 and control words 8 .. 15 is ?0?. the reset default state for control words 6 a nd 7 is vendor specific. every time the de vice is reset, its default state is restored. stopping the clocks (ck = ck = low) to put the device in low-power mode will not alter the control word settings.
1.35v/1.5v registering clock driver with parity test and quad chip select 55 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature control word decoding wi th quadcs mode disabled signal control word symbol dcs0 dcs1 dba2 da2 da1 da0 meaning none n/a h x x x x x no control word access none n/a x h x x x x no control word access control word 0 rc0 l l l l l l global features control word control word 1 rc1 l l l l l h clock driver enable control word control word 2 rc2 l l l l h l timing control word control word 3 rc3 l l l l h h ca signals driver characteristics control word control word 4 rc4 l l l h l l control signals driver characteristics control word control word 5 rc5 l l l h l h ck driv er characteristics control word control word 6 rc6 l l l h h l reserved, free to use by vendor control word 7 rc7 l l l h h h reserved, free to use by vendor control word 8 rc8 l l h l l l additional ibt setting control word control word 9 rc9 l l h l l h power saving settings control word control word 10 rc10 l l h l h l encoding for rdimm operating speed control word 11 rc11 l l h l h h encoding for rdimm operating v dd control word 12 rc12 l l h h l l reserved for future use control word 13 rc13 l l h h l h reserved for future use control word 14 rc14 l l h h h l reserved for future use control word 15 rc15 l l h h h h reserved for future use
1.35v/1.5v registering clock driver with parity test and quad chip select 56 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature control word decoding wi th quadcs mode enabled signal control word symbol dcs[3:0] dba2 da2 da1 da0 meaning none n/a hxhx x x x x no control word access none n/a hxxh x x x x none n/a xhhx x x x x none n/a xhxh x x x x none n/a hlll x x x x ilegal input states none n/a lhll x x x x none n/a llhl x x x x none n/a lllh x x x x control word 0 rc0 llhh or hhll or llll l l l l global features control word control word 1 rc1 l l l h clock driver enable control word control word 2 rc2 l l h l timing control word control word 3 rc3 l l h h ca signals driver characteristics control word control word 4 rc4 l h l l control signals driver characteristics control word control word 5 rc5 l h l h ck driver characteristics control word control word 6 rc6 l h h l reserved, free to use by vendor control word 7 rc7 l h h h reserved, free to use by vendor control word 8 rc8 h l l l additional ibt setting control word control word 9 rc9 h l l h power saving settings control word control word 10 rc10 h l h l encodi ng for rdimm operating speed control word 11 rc11 h l h h encoding for rdimm operating v dd control word 12 rc12 h h l l reserved for future use control word 13 rc13 h h l h reserved for future use control word 14 rc14 h h h l reserved for future use control word 15 rc15 h h h h reserved for future use
1.35v/1.5v registering clock driver with parity test and quad chip select 57 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature control word functions the following sections describe th e contents of each control word. rc0: global features control word output inversion: when output inversion is disabled, all a an d b output drivers of the sste32882hlb are driven to the same levels. output inversion may be enabled to conserve power, reducing simultaneous switching output currents in the sste32882hlb. when output inversion is enabled, all a outputs will follow the equivalent inputs, however the following b outputs will be driven to the complement of the matching a output: qba03-qba9, qba11, qba13 - qba15, qbba0 - qbba2. output inversion does not affect sste32882hlb control word programming. output floating refers to allowing many a/b outputs to enter a hi -z state when they are not bein g used. this is to conserve power when the outputs are resistively terminated to a voltage (e.g., v dd , v tt , or v ss ). when output floating is enabled, the following outputs (on both matching a and b outputs) are hi-z when not actively driven: qxan, qxban, qxras , qxcas , and qxwe . output floating is independent of output invers ion and does not affect sste32882hlb control word programming. input definition encoding dba1 dba0 da4 da3 x x x 0 output inversion output inversion enabled x x x 1 output inversion disabled x x 0 x float outputs float disabled x x 1 x float enabled x 0 x x a outputs disabled a outputs enabled x 1 x x a outputs disabled 0 x x x b outputs disabled b outputs enabled 1 x x x b outputs disabled output inversion functional diagram qaxxx output qbxxx output dxxx input rc0-da3 control bit register
1.35v/1.5v registering clock driver with parity test and quad chip select 58 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature a or b output disable allows the use of the sste32882hlb in reduced parts count applications such as ddr3 mini-rdimms. when output disable is asserted , all outputs on the corresponding side of the re gister, including the clock drivers, remain in hi-z at all times. when rc0[dba0] = 1, all a-side q-outputs and y1 and y3 outputs will be disabled. when rc0[dba1] = 1, all b-side q-outputs and y0 and y2 outputs will be disabled. when rc0[dba0] = 1 and rc0[dba1] = 1, all a-side and b-side q-outputs and yn outputs will be disabled. rc1: clock driver enable control word output clocks may be individually turned on or off to conser ve power. the system must r ead the module spd to determine which clock outputs are used by the module. the pll remains locked on ck/ck unless the system stops the clock inputs to the sste32882hlb to enter the lowest power mode. rc2: timing control word input definition encoding dba1 dba0 da4 da3 x x x 0 disable y0/y0 clock y0/y0 clock enabled xxx1 y0/y0 clock disabled x x 0 x disable y1/y1 clock y1/y1 clock enabled xx1x y1/y1 clock disabled x 0 x x disable y2/y2 clock y2/y2 clock enabled x1xx y2/y2 clock disabled 0 x x x disable y3/y3 clock y3/y3 clock enabled 1xxx y3/y3 clock disabled input definition encoding dba1 dba0 da4 da3 xxx0 address- and command-nets pre-launch (control signals qxcke, qxcs, qxodt do not apply) standard (1/2 clock) x x x 1 address and command nets pre-launch (3/4 clock) xx0x 1t/3t output timing 1t timing xx1x 3t timing (1) 1 there is no floating once 3t timing is activated. x0xx input bus termination (2) 2 if mirror is ?high? then input bus termination (i bt) is turned off, or on all inputs except the dcsn and dodtn inputs. 100 ? x 1 x x 150 ? 0xxx frequency band select operation (frequency band 1) 1 x x x test mode (frequency band 2)
1.35v/1.5v registering clock driver with parity test and quad chip select 59 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature the ibt control is also located in this control word, with two options of 100 ? or 150 ? which can be selected to adapt to different system scenarios. at power-up, the sste32882hlb ibt defaults to 100 ? . the system controlle r can reprogram the termination resistance to 150 ? by setting this bit. only the dan, dban, dras , dcas , dwe , dcsn , dodtn, dcken, and par_in inputs have the ibt. the ck, ck , fbin, fbin , reset, and mirror inputs do not have ibt. if mirror is ?high? then it is assumed the register is locat ed on the back side of a modu le where two registers are tied together on the input side. in this case, for the register on th e back side, the ibt are turned off on all inputs except the dc sn and dodtn inputs. the following diagram illustrates the pre-la unch feature whereby double lo aded nets in a 2-rank configuration can be driven with an earlier signal compared to output clock and control in order to compensate for the slow er signal travel speed. this timing applies at all supported frequencies. effective ibt tolerance requirement min max total effective ibt value tolerance 1 1 example: for 100 ohm ibt, min = 90 ohms, max = 110 ohms -10% +10% mismatch tolerance between r-ibt-up and r-ibt-down max mismatch tolerance between r-ibt-up and r-ibt-down 1 1 (1 - r-ibt-up/r-ibt-down) *100% < abs(5%) abs(5%)
1.35v/1.5v registering clock driver with parity test and quad chip select 60 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature standard versus address and co mmand-nets pre-launch timing 1 ck and yn left out for better visibility. 2 rca0 is re-driven command address signal based on input ca0. output driver character istics are separately controlled for outputs that are often loaded with twice as many drams as the other outputs. outputs are grouped as follows: ? ca signals =qxa0-qxan, qxba0-qxban, qxras , qxcas , qxwe ? control signals = qxcsn , qxcken, qxodtn ? ck = yn .. yn ck (1) dcs c/a qxcsx , qn(c/a) qn(c/a) input standard c/a yn (1) qxckex, qxodtx qxcsx, qxckex, qxodtx n n+1 n+2 n+3 n+4 n+5 n+6 pre- launch ca0 3/4 clock qn(c/a) pre-launch time rca0 (2) rca0 yn (1)
1.35v/1.5v registering clock driver with parity test and quad chip select 61 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature rc3: ca signals driver ch aracteristics control word rc4: control signals driver characteristics control word input definition encoding dba1 dba0 da4 da3 xx00 command/address driver-a outputs light drive (4 or 5 dram loads) x x 0 1 moderate drive (8 or 10 dram loads) x x 1 0 strong drive (16 or 20 dram loads) xx11 reserved 00xx command/address driver-b outputs light drive (4 or 5 dram loads) 0 1 x x moderate drive (8 or 10 dram loads) 1 0 x x strong drive (16 or 20 dram loads) 11xx reserved input definition encoding dba1 dba0 da4 da3 xx00 control driver-a outputs light drive (4 or 5 dram loads) x x 0 1 moderate drive (8 or 10 dram loads) xx10 reserved xx11 reserved 00xx control driver-b outputs light drive (4 or 5 dram loads) 0 1 x x moderate drive (8 or 10 dram loads) 10xx reserved 11xx reserved
1.35v/1.5v registering clock driver with parity test and quad chip select 62 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature rc5: ck driver charac teristics control word rc8: additional ibt setting control word input definition encoding dba1 dba0 da4 da3 xx00 clock y1, y1 , y3, and y3 output drivers light drive (4 or 5 dram loads) x x 0 1 moderate drive (8 or 10 dram loads) x x 1 0 strong drive (16 or 20 dram loads) xx11 reserved 00xx clock y0, y0 , y2, and y2 output drivers light drive (4 or 5 dram loads) 0 1 x x moderate drive (8 or 10 dram loads) 1 0 x x strong drive (16 or 20 dram loads) 11xx reserved input definition encoding dba1 dba0 da4 da3 x000 ibt compatibility settings ibt as defined in rc2 0xxx mirror mode ibt off when mirror is high 1 1 if mirror is high, then input bus termination (ibt) is turned off on all inputs, except dcsn and dod- tn inputs. 1xxx ibt on when mirror is high 2 2 when dba0 = 1, da4 = 1, or da3 = 1, ibt on all inputs is turned off no matter what the dba1 setting may be. x001 input bus termination 1 reserved x010 200 ? x011 reserved x100 300 ? x101 reserved x110 reserved x111 off 3 3 with this setting, no matter what the logic level of the mirror input pin may be, ibt on all inputs (in- cluding dcsn and dodtn) is turned off.
1.35v/1.5v registering clock driver with parity test and quad chip select 63 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature rc9: power saving settings control word the sste32882hlb features a weak drive mode, which is a variant of the floating mode set in rc0. if bit da4 of rc0 is set to ?1?, then bit da3 of rc9 selects between floating mode and weak drive mode. the sste32882hlb register supports different power down mode s. by default, the power down feature is disabled (rc9[dba1]=0). the register ignores cke power down mode setting when this function is disabled. if the cke power down mode is enabled (rc9[dba1]=1), then power down is invoked once both dcke0 and dcke1 are low. bit dba0 selects how ibt and odt behaves. rc10: encoding for rdimm operating speed the encoding value is used to inform the register the operating speed that it is bei ng run at in a system. it is not an indicat or of how fast or slow a register can run input definition encoding dba1 dba0 da4 da3 xxx0 weak drive mode floating xxx1 typical weak drive enabled 1 weak driver impedance: 70 ? (min), 100 ? (nom), 120 ? (min) 1 to get optimum power saving while k eeping the vil dc (max) limit for sd ram, the weak drive mode impedance should be 70 ? (min), 100 ? (nom), 120 ? (min) . xx0x reserved reserved xx1x reserved 10xx cke power down mode cke power down with ibt on, qxodt is a function of dxodt 1 1 x x cke power down with ibt off, qxodt held low 0xxx cke power down mode enable disabled 1xxx enabled input definition encoding dba1 dba0 da4 da3 x000 f < 800 mts ddr3-800 (default) x001 800 mts < f < 1066 mts ddr3-1066 x0101066 mts < f < 1333 mts ddr3-1333 x0111333 mts < f < 1600 mts ddr3-1600 x100 reserved reserved x101 reserved reserved x110 reserved reserved x111 reserved reserved
1.35v/1.5v registering clock driver with parity test and quad chip select 64 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature rc11: operating voltage v dd control word rc11 is used to inform the sste32882hlb under what operating voltage v dd will be used. the register can use the information to optimize functionality and performance lv condition. input definition encoding dba1 dba0 da4 da3 xx00 register v dd operating voltage ddr3 normal 1.5v mode xx01 ddr3l 1.35v mode xx10 reserved xx11 reserved 00xx reserved 01xx reserved 10xx reserved 11xx reserved
1.35v/1.5v registering clock driver with parity test and quad chip select 65 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature test circuits and switching waveforms parameter measurement information all input pulses are supplied by generators having the following characteristics: 300mhz ?? prr ? 810 mhz; zo = 50 ? ; input slew rate = 1 v/ns 20%, unless otherwis e specified. the outputs are measured one at a time with one transition per measurement. qn and yn load circuit for propa gation delay and slew measurement 1 c l is parasitic (probe and jig capacitance). voltage waveforms; propagation delay times v tt = v dd /2 v icr cross point voltage v i ( p - p ) = 500mv (1.5v operation) or 450mv (1.35v operation) t pdm 1, t pdm 2 the larger number of both has to be taken when performing t pdm max measurement, the sm aller number of both has to be taken when performing t pdm min measurement. c l <2.5pf (1) dut out te s t p o i n t ck inputs t l = 50 ? r l = 100 ? te s t p o i n t te s t p o i n t v tt r l = 50 ? ck ck trace delay matched on load board v tt q output v tt ck ck t pdm 1t pdm 2 v icr v icr v i ( p - p )
1.35v/1.5v registering clock driver with parity test and quad chip select 66 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature voltage waveforms address floating refer to ?calculating the virtual v ref crossing point?. enabling and disabling the ca outputs must not violate dram setup and hold time requirements. therefore a t dis transition may not occure earlier than a re gular (hl/lh) transition and a t en transition may not occure la ter than a regular (hl/lh) transition. regular transition s are measured between ck/ck and ca/v tt crossings however a v tt crossing is not available in the state where the outputs ar e hi-z. to allow a correct and not overl y conservative measurement a virtual v tt crossing point is defined below. the calculation of the virtual v tt crossing point is shown in the figure, ?calculating the virtual v tt crossing point?. the voltage levels for y xa and y xb are measured from v tt (v dd /2) and should be selected such that the region between t 1 and t 2 covers a linear range and represents a ty pical slope of the waveform within the transition area. they have to be used signed in the formula. outputs yn yn t dis t en v ox v ox v od ck ck dcsn qxcsn virtual v tt crossing *
1.35v/1.5v registering clock driver with parity test and quad chip select 67 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature calculating the virtual v tt crossing point t dis t en = t 1a + y 1a (t 1a -t 2a )/(y 2a -y 1a ) v ol v oh v tt v tt y 1b y 2b actual waveform y 1b y 2b t 2b t 1b u ck =u ck y 2a y 2a y 1a y 1a t en t 2a t 1a yn yn t dis = t 1b + y 1b (t 1b -t 2b )/(y 2b -y 1b ) v tt =v dd /2
1.35v/1.5v registering clock driver with parity test and quad chip select 68 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature voltage waveforms, high-to- low slew rate measurement voltage waveforms, low-to-h igh slew rate measurement error output load circuit and vo ltage measurement information all input pulses are supplied by generators having the following characteristics: 300mhz ? prr ? 810mhz; zo = 50 ? ; input slew rate = 1 v/ns 20%, unless otherwise specified. load circuit, errout outputs 1 c l includes probe and jig capacitance. ac level for slew rate measurement ddr3-800/1066/1333/1600 ac level (1.5v) 150mv ac level (1.35v) 135mv dv_f dt_f + ac level - ac level v oh v ol output v tt dv_r dt_r + ac level - ac level v oh v ol output v tt r l =50 r l =10pf dut out v dd te s t p o i n t see note (1)
1.35v/1.5v registering clock driver with parity test and quad chip select 69 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature the output driver characteristics are separately controlled for out puts that are often loaded with twice as many drams as the o ther outputs. outputs are grouped as follows: ? ca signals =qxa0-qxan, qxba0-qxban, qxras , qxcas , qxwe ? control signals = qxcsn , qxcken, qxodtn ? ck = yn .. yn the register output slew-rate & r-on fo r each drive strength as shown below. output slew-rate & r-on (targets) drive settings output driver r-on targets (ohms) output slew-rate (v/ns) ddr3-800/1066/1333 ddr3-1600 ddr3l-800/1066/1333 /1600 min nom max min max min max min max light 22 26 30 2 7 2 5.5 1.8 5.0 moderate 16 19 22 2 7 2 5.5 1.8 5.0 strong 12 14 16 2 7 2 5.5 1.8 5.0
1.35v/1.5v registering clock driver with parity test and quad chip select 70 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature measurement requirement for tstaoff and tdynoff voltage waveforms, reset to errout t plh measurement ck ck yn yn t staoff(min) 1 1. t staoff = propagation delay for clock signal (rising ck i nput clock edge to rising yn output clock edge). t dynoff 2 2. t dynoff = maximum t staoff variation over voltage and temperature. this includes all sources of jitter and drift (e.g.thermal noise, supply noise, voltage/temperature drift, ssc tracking, sso, etc) except reference clock noise. t staoff 1 t staoff(max) 1 0.65v 0v 0v v oh v dd /2 v dd t plh output input cmos reset open drain errout
1.35v/1.5v registering clock driver with parity test and quad chip select 71 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature voltage waveforms, ck to errout t hl measurement v tt = v dd /2 voltage waveforms, ck to errout t lh measurement recommended filtering for th e analog power supply (av dd ) place the 2200pf capacito r close to the pll. use a wide trace for the pll analog power and ground. connect pll and caps to agnd trace and connect trace to one gnd via (farthest from pll). bead is 0.8 ? dc max, 600 ? at 100mhz. open drain output errout v id ck ck v icr t lh v oh v ol v tt 0.65v 0v v oh t lh open drain output errout v id ck ck v icr v ddq gnd via card via card bead 4.7uf 0.1uf 2200pf av dd agnd sstef32882 1 ? r1 sste32882
1.35v/1.5v registering clock driver with parity test and quad chip select 72 sste32882hlb 7201/14 sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ordering information xx temp. shipping 8 tape and reel commercial (0 o c to +70 o c) blank range xx package xxxx device low profile, fine pitch, ball grid array - green akg carrier sste type bkg thin profile, fine pitch, ball grid array - green (0.65mm ball pitch, 11 x 20 grid, 8.0mm x 13.5mm (0.65mm ball pitch, 8 x 22 grid, 6.0mm x 15mm) 32882hlb registering clock driver with parity test
corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) for sales 800-345-7015 408-284-8200 fax: 408-284-2775 discover what idt know-how can do for you. contact: www.idt.com sste32882hlb 1.35v/1.5v registering clock driver with parity test and quad chip select commercial temperature ?

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